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| confidential preliminary encore? ii low-speed usb peripheral controlle r cy7c63310 cy7c638xx cy7c639xx cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document 38-08035 rev. *c revised december 13, 2004 1.0 features ? encore ? ii usb??enhanced component reduction? ? crystalless oscillator with support for an external crystal or resonator. the internal oscillator eliminates the need for an external crystal or resonator ? internal 3.3v regulator and internal usb pull-up resistor ? configurable io for real -world interf ace without external components ? usb specification compliance ? conforms to usb specification, version 2.0 ? conforms to usb hid sp ecification, version 1.1 ? supports one low-speed usb device address ? supports one control endpoint and two data endpoints ? integrated usb transceiver ? enhanced 8-bit microcontroller ? harvard architecture ? m8c cpu speed can be up to 24 mhz or sourced by an external crystal, resonator, or signal ? internal memory ? up to 256 bytes of ram ? up to eight kbytes of flash including eerom emulation ? interface can auto-configure to operate as ps/2 or usb ? no external components for switching between ps/2 and usb modes ? no gpio pins needed to manage dual-mode capability ? low power consumption ? typically 10 ma at 6 mhz ? 10-ua sleep ? in-system re-programmability ? allows easy firmware update ? general-purpose i/o ports ? up to 36 general purpose i/o (gpio) pins ? high current drive on gpio pins. configurable 8- or 50-ma/pin current sink on designated pins ? each gpio port supports high-impedance inputs, configurable pull-up, open drain output, cmos/ttl inputs, and cmos output ? maskable interrupts on all i/o pins ? 125-ma 3.3v voltage regulator can power external 3.3v devices ? 3.3v i/o pins ? 4 i/o pins with 3.3v logic levels ? each 3.3v pin supports high-impedance input, internal pull-up, open drain output or traditional cmos output ? spi serial communication ? master or slave operation ? configurable up to 2-mbit/second transfers ? supports half duplex single data line mode for optical sensors ? 2-channel 8-bit or 1-channel 16-bit capture timer. capture timers registers store both rising and falling edge times ? two registers each for two input pins ? separate registers for rising and falling edge capture ? simplifies interface to rf inputs for wireless applications ? internal low-power wake-up timer during suspend mode ? periodic wake-up with no external components ? programmable interval timer interrupts ? reduced rf emissions at 27 mhz and 96 mhz ? advanced development tools based on cypress microsystems psoc? tools ? watchdog timer (wdt) ? low-voltage detection with user-configurable threshold voltages ? improved output drivers to reduce emi ? operating voltage from 4.0v to 5.25vdc ? operating temperature from 0?70c ? available in 16/18/24/40-pin pdip, 16/18/24-pin soic, 24- pin qsop, 28/48-pin ssop, and die form ? industry standard programmer support 1.1 applications the CY7C633XX/cy7c638xx/cy7c639xx is targeted for the following applications: ? pc hid devices ? mice (optomechanical, optical, trackball) ? keyboards ?gaming ? joysticks ? game pads ? console keyboards ? general purpose ? barcode scanners ? pos terminal ? consumer electronics ?toys ? remote controls
confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 2 of 70 2.0 introduction cypress has reinvented its leadership position in the low- speed usb market with a new family of innovative microcon- trollers. introducing encore ii usb ? ?enhanced component reduction.? cypress has leveraged its design expertise in usb solutions to advance its family of low-speed usb micro- controllers, which enable peripheral developers to design new products with a minimum number of components. the encore ii usb technology builds on to the encore family. the encore family has an integrated oscillator that eliminates the external crystal or resonator reducing overall cost. also integrated into this chip are other external components commonly found in low-speed usb applications such as pull- up resistors, wake-up circuitry, and a 3.3v regulator. all of this adds up to a lower system cost. the encore ii is 8-bit flash-programmable microcontroller with integrated low-speed usb interface. the instruction set has been optimized specifically for usb and ps/2 operations, although the microcontrollers can be used for a variety of other embedded applications. the encore ii features up to 36 general-purpose i/o (gpio) pins to support usb, ps/2 and other applications. the i/o pins are grouped into five ports (port 0 to 4). the pins on port 0 and port 1 may each be configured individually while the pins on ports 2, 3, and 4 may only be configured as a group. each gpio port supports high-impedance inputs, configurable pull- up, open drain output, cmos/ttl inputs, and cmos output with up to five pins that s upport programmable drive strength of up to 50-ma sink current. gpio port 1 features four pins that interface at a voltage level of 3.3 volts. additionally, each i/o pin can be used to generate a gp io interrupt to the microcon- troller. each gpio port has its own gpio interrupt vector with the exception of gpio port 0. gpio port 0 has three dedicated pins that have independent in terrupt vectors (p0.2 - p0.4). the encore ii features an internal oscillator. with the presence of usb traffic, the internal oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). optionally, an external 12-mhz or 24-mhz crystal can be used to provide a higher precision reference for usb operation. the clock generator provides the 12-mhz and 24-mhz clocks that remain internal to the microcontroller. the encore ii has up to eight kbytes of flash for user?s code and up to 256 bytes of ram for stack space and user variables. in addition, the encore ii includes low-voltage reset logic, a watchdog timer, a vectored interr upt controller, a 16-bit free- running timer, and capture timers. the low-voltage reset (lvr) logic detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at flash address 0x0000. the lvr may reset the parts when vcc drops below a programmable trip voltage or it may be configurable to generate a lvr/por interrupt to inform the processor about the low-voltag e event. the watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. the microcontroller supports 23 maskable interrupts in the vectored interrupt controller. interrupt sources include a usb bus reset, lvr/por, a programmable interval timer, a 1.024- ms output from the free running timer, three usb endpoints, two capture timers, five gpio ports, three gpio pins, two spi, a 16-bit free running timer wrap, an internal wake-up timer, and a bus active interrupt. the wake-up timer causes periodic interrupts when enabled. the usb endpoints interrupt after a usb transaction complete is on the bus. the capture timers interrupt whenever a new timer value is saved due to a selected gpio edge event. a to tal of eight gpio interrupts support both ttl or cmos thresholds. for additional flexi- bility, on the edge sensitive gpio pins, the interrupt polarity is programmable to be either rising or falling. the free-running 16-bit timer provides two interrupt sources: the programmable interval timer with 1 microsecond resolution and the 1.024 ms outputs. the timer can be used to measure the duration of an event under firmware control by reading the timer at the start and at the end of an event, then calculating the difference between the two values. the two 8-bit capture timers save a programmable 8-bit range of the free-running timer when a gpio edge occurs on the two capture pins (p0.0, p0.1). the two 8-bit captures can be ganged into a single 16- bit capture. the encore ii includes an integrated usb serial interface engine (sie) that allows the chip to easily interface to a usb host. the hardware supports one usb device address with three endpoints. the usb d+ and d? pins can alternately be used as ps/2 sclk and sdata signals so that products can be designed to respond to either usb or ps/2 modes of operation. ps/2 operation is supported with internal pull-up resistors on sclk and sdata and an interrupt to signal the start of ps/2 activity. in usb mode the integrated pull-up resistor on d- can be controlled under firmware. no external components are necessary for dual usb and ps/2 systems, and no gpio pins need to be dedicated to switching between modes. slow edge rates operate in both modes to reduce emi. the encore ii supports in-system programming by using the d+ and d- pins as the serial programming mode interface. the programming protocol is not usb. 3.0 conventions in this document, bit positions in the registers are shaded to indicate which members of the en core ii family implement the bits. available in all encore ii family members cy7c639xx and cy7c638xx only cy7c639xx only confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 3 of 70 4.0 logic block diagram figure 4-1. CY7C633XX/cy7c638xx/cy7c639xx block diagram internal 24 mhz oscillator 3.3v regulator clock control crystal oscillator por / low-voltage detect watchdog timer ram up to 256 byte m8c cpu flash up to 8k byte 16 extended i/o pins low-speed usb/ps2 transceiver and pull-up 16 gpio pins wakeup timer capture timers 12-bit timer 4 3vio/spi pins vdd interrupt control low-speed usb sie confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 4 of 70 5.0 packages/pinouts figure 5-1. package configurations 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.0 p2.0 p1.5/smosi p1.3/ssel p3.1 p3.0 v dd p1.2/vreg p1.1/sclk/d- p1.0/sdata/d+ 14 p1.4/sclk 10 p2.1 nc v ss 12 13 7 8 int0/p0.2 p0.1 24 23 p1.7 p1.6/smiso 24-pin qsop cy7c63823 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 ssel/p1.3 sclk/p1.4 smosi/p1.5 smiso/p1.6 p0.7 tio0/p0.5 p1.2/vreg p1.1/sclkd/d- p1.0/sdata/d+ p0.0 p0.1 p0.2/int0 18-pin pdip v dd 9 tio1/p0.6 int2/p0.4 p0.3/int1 cy7c63813 5 14 p1.7 v ss 1 2 3 4 6 7 8 9 10 11 13 14 16 15 ssel/p1.3 sclk/p1.4 smosi/p1.5 smiso/p1.6 tio1/p0.5 int1/p0.3 p1.2/vreg p1.1/sclk/d- p1.0/sdata/d+ p0.1 p0.2/int0 p0.0 16-pin pdip v dd int2/p0.4 5 12 p0.6/tio1 v ss top view cy7c63310 cy7c63801 16-pin pdip 1 2 3 4 6 7 8 9 10 11 13 14 16 15 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.1 v ss p1.6/smiso p1.4/sclk p1.3/ssel p1.1/sclk/d- p1.0/sdata/d+ v dd 16-pin soic p1.5/smosi p0.0 5 12 p0.2/int0 p1.2/vreg cy7c63310 cy7c63801/3 16-pin soic 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.2/int0 p0.0 p1.7 p1.5/smosi p1.4/sclk p1.2/vreg v dd p1.1/sclk/d- 18-pin soic p1.6/smiso 9 p0.1 v ss p1.0/sdata/d+ cy7c63813 5 14 p0.3/int1 p1.3/ssel 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 p3.0 p3.1 sclk/p1.4 smosi/p1.5 smiso/p1.6 p1.7 p0.7 tio0/p0.5 v dd p2.0 p1.0/sdata/d+ v ss p0.0 p2.1 p0.1 p0.2/int0 14 p1.1/sclk/d- 10 tio1/p0.6 int2/p0.4 p0.3/int1 12 13 7 8 nc nc 24 23 p1.3/ssel p1.2/vreg 24-pin pdip cy7c63823 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.0 p2.0 p1.6/smiso p3.0 p1.4/sclk p3.1 p1.2/vreg p1.3/ssel v dd p1.1/sclk/d- 14 p1.5/smosi 10 p2.1 v ss p1.0/sdata/d+ 12 13 7 8 int0/p0.2 p0.1 24 23 nc p1.7 24-pin soic cy7c63823 1 2 3 4 5 6 9 11 19 20 21 22 23 24 26 25 v dd p2.7 p2.6 p2.5 p2.4 p0.7 int2/p0.4 int0/p0.2 p3.6 p1.6/smiso p3.4 p1.7 p1.4/sclk p1.5/smosi p1.3/ssel p1.2/vreg 18 p3.5 10 int1/p0.3 clkout/p0.1 v dd 12 17 7 8 tio1/p0.6 tio0/p0.5 28 27 v ss p3.7 28-pin ssop cy7c63903 15 16 p1.1/sclk/d- p1.0/sdata/d+ 13 clkin/p0.0 14 v ss confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 5 of 70 5.1 pinouts assignments figure 5-1 package configurations (continued) 1 2 3 4 5 6 9 11 nc nc nc nc v dd p4.1 p2.6 p2.4 10 p2.5 p2.3 12 7 8 p4.0 p2.7 48-pin ssop cy7c63923 13 14 15 16 17 18 21 23 p2.2 p2.1 p2.0 p0.7 p0.6/tio1 p0.5/tio0 p0.2/int0 p0.0/clkin 22 p0.1/clkout v ss 24 19 20 p0.4/int2 p0.3/int1 27 28 29 30 31 32 34 33 p3.0 p1.4/sclk p1.6/smiso p1.5/smosi p1.2/vreg p1.3/ssel v dd p1.1/sclk/d- 26 p1.7 p1.0/sdata/d+ 25 36 35 p3.2 p3.1 39 40 41 42 43 44 46 45 nc p4.2 v ss p4.3 p3.6 p3.7 p3.5 p3.4 38 nc p3.3 37 48 47 nc nc 1 2 3 4 5 6 9 11 v dd p4.1 p2.6 p2.4 10 p2.5 p2.3 12 7 8 p4.0 p2.7 40-pin pdip cy7c63913 13 14 15 16 17 18 p2.2 p2.1 p2.0 p0.7 p0.6/tio1 p0.5/tio0 p0.2/int0 p0.0/clkin p0.1/clkout v ss 19 p0.4/int2 p0.3/int1 21 22 23 24 26 25 p3.0 p1.4/sclk p1.6/smiso p1.5/smosi p1.2/vreg p1.3/ssel v dd p1.1/sclk/d- p1.7 p1.0/sdata/d+ 28 27 p3.2 p3.1 31 32 33 34 35 36 38 37 p4.2 v ss p4.3 p3.6 p3.7 p3.5 p3.4 30 p3.3 29 40 39 20 40 cy7c63923-xc die top view 6 5 4 3 2 1 44 46 47 48 41 42 43 35 39 38 37 36 34 33 32 31 30 29 28 27 22 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 p4.1 p3.6 vdd nc p4.3 nc nc nc vss nc nc nc p4.2 p3.7 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 vdd p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2/vreg p1.1/sclk/d- p1.0/sdata/d+ vss p0.0/clkin p0.1/clkout p0.2/int0 p0.3/int1 p0.4/int2 p0.5/tio0 p0.6/tio1 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p4.0 table 5-1. pin assignments 48 ssop 40 pdip 28 ssop 24 qsop 24 soic 24 pdip 18 sioc 18 pdip 16 soic 16 pdip die pad name description 7 3 7 p4.0 gpio port 4 ? configured as a group (nibble) 62 6p4.1 42 38 42 p4.2 43 39 43 p4.3 34 30 18 1 34 p3.0 gpio port 3 ? configured as a group (byte) 35 31 20 19 2 35 p3.1 36 32 19 36 p3.2 37 33 37 p3.3 38 34 24 38 p3.4 39 35 25 39 p3.5 40 36 26 40 p3.6 41 37 27 41 p3.7 15 11 11 11 18 15 p2.0 gpio port 2 ? configured as a group (byte) 14 10 10 10 17 14 p2.1 13 9 13 p2.2 12 8 12 p2.3 11 7 5 11 p2.4 10 6 4 10 p2.5 953 9p2.6 842 8p2.7 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 6 of 70 25 21 15 14 13 20 10 15 9 13 25 p1.0/sdata/ d+ gpio port 1 bit 0 / ps2 io data / usb d+ 26 22 16 15 14 21 11 16 10 14 26 p1.1/sclk/ d- gpio port 1 bit 1 / ps2 io clock / usb d- 28 24 18 17 16 23 13 18 12 16 28 p1.2/vreg gpio port 1 bit 2 ? configured individually. 3.3v if regulator is enabled (add reference) 29 25 19 18 17 24 14 1 13 1 29 p1.3/ssel gpio port 1 bit 3 ? configured individually. alternate function is ssel signal of the spi bus ttl voltage thresholds 30 26 20 21 20 3 15 2 14 2 30 p1.4/sclk gpio port 1 bit 4 ? configured individually. alternate function is sclk signal of the spi bus ttl voltage thresholds 31 27 21 22 21 4 16 3 15 3 31 p1.5/smosi gpio port 1 bit 5 ? configured individually. alternate function is smosi signal of the spi bus ttl voltage thresholds 32 28 22 23 22 5 17 4 16 4 32 p1.6/smiso gpio port 1 bit 6 ? configured individually. alternate function is smiso signal of the spi bus ttl voltage thresholds 33 29 23 24 23 6 18 5 33 p1.7 gpio port 1 bit 7 ? configured individually. 23 19 13 9 9 16 8 13 7 11 23 p0.0/clkin gpio port 0 bit 0 ? configured individually. on cy7c639xx, optional clock in when external crystal oscillator is disabled or crystal input when external crystal oscil- lator is enabled. on cy7c638xx and cy7c63310, oscil- lator input when configured as clock in 22 18 12 8 8 15 7 12 6 10 22 p0.1 / clkout gpio port 0 bit 1? configured individually on cy7c639xx, optional clock out when external crystal oscillator is disabled or crystal output drive when external crystal oscillator is enabled. on cy7c638xx and cy7c63310, oscil- lator output when configured as clock out. 21 17 11 7 7 14 6 11 5 9 21 p0.2/int0 gpio port 0 bit 2 ? configured individually optional rising e dge interrupt int0 20 16 10 6 6 13 5 10 4 8 20 p0.3/int1 gpio port 0 bit 3 ? configured individually optional rising e dge interrupt int1 19 15 9 5 5 12 4 9 3 7 19 p0.4/int2 gpio port 0 bit 4 ? configured individually optional rising e dge interrupt int2 18 14 8 4 4 11 3 8 2 6 18 p0.5/tio0 gpio port 0 bit 5 ? configured individually alternate function timer capture inputs or timer output tio0 17 13 7 3 3 10 2 7 1 5 17 p0.6/tio1 gpio port 0 bit 6 ? configured individually alternate function timer capture inputs or timer output tio1 16 12 6 2 2 9 1 6 16 p0.7 gpio port 0 bit 7 ? configured individually not in 16 pin pdip or soic package 1,2,3,4 1 1 7 1,2, 3,4 nc no connect table 5-1. pin assignments (continued) 48 ssop 40 pdip 28 ssop 24 qsop 24 soic 24 pdip 18 sioc 18 pdip 16 soic 16 pdip die pad name description confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 7 of 70 6.0 cpu architecture this family of microcontrollers is based on a high performance, 8-bit, harvard architecture microprocessor. five registers control the primary operation of the cpu core. these registers are affected by various instructions, but are not directly acces- sible through the register space by the user. the 16-bit program counter register (cpu_pc) allows for direct addressing of the full eight kbytes of program memory space. the accumulator register (cpu_a) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. the index register (cpu_x) holds an offset value that is used in the indexed addressing modes. typically, this is used to address a block of data within the data memory space. the stack pointer register (cpu_sp) holds the address of the current top-of-stack in the data memory space. it is affected by the push, pop, lcall, call, reti, and ret instructions, which manage the software stack. it can also be affected by the swap and add instructions. the flag register (cpu_f) has three status bits: zero flag bit [1]; carry flag bit [2]; supervisory state bit [3]. the global interrupt enable bit [0] is used to globally enable or disable interrupts. the user cannot manipulate the supervisory state status bit [3]. the flags are affe cted by arithmetic, logic, and shift operations. the manner in which each flag is changed is dependent upon the instruction being executed (i.e., and, or, xor). see table 8-1 . 45,46, 47,48 12 24 8 45, 46, 47, 48 nc no connect 51 5v dd power 27 23 1 16 15 22 12 17 11 15 27 44 40 ? ? ? ? 44 v ss 24 20 28 13 12 19 9 14 8 12 24 table 5-1. pin assignments (continued) 48 ssop 40 pdip 28 ssop 24 qsop 24 soic 24 pdip 18 sioc 18 pdip 16 soic 16 pdip die pad name description table 6-1. cpu registers and mnemonics register mnemonic flags cpu_f program counter cpu_pc accumulator cpu_a stack pointer cpu_sp index cpu_x confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 8 of 70 7.0 cpu registers 7.1 flags register the flags register can only be set or reset with logical instruction. 7.1.1 accumulator register 7.1.2 index register table 7-1. cpu flags register (cpu_f) [0xf7] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved reserved xio super carry zero global ie read/write ? ? ? r/w r rw rw rw default 00000010 bit [7:5]: reserved bit 4: xio set by the user to select between the register banks 0 = bank 0 1 = bank 1 bit 3: super indicates whether the cpu is executing us er code or supervisor code. (this code cannot be accessed directly by the user) 0 = user code 1 = supervisor code bit 2: carry set by cpu to indicate whether there has been a ca rry in the previous logi cal/arithmetic operation 0 = no carry 1 = carry bit 1: zero set by cpu to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = not equal to zero 1 = equal to zero bit 0: global ie determines whether all interrupts are enabled or disabled 0 = disabled 1 = enabled table 7-2. cpu accumulator register (cpu_a) bit # 7 6 5 4 3 2 1 0 field cpu accumulator [7:0] read/write ???????? default 00000000 bit [7:0]: cpu accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic in struction that uses a source addressing mode table 7-3. cpu x register (cpu_x) bit # 7 6 5 4 3 2 1 0 field x [7:0] read/write ???????? default 00000000 bit [7:0]: x [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 9 of 70 7.1.3 stack pointer register 7.1.4 cpu program counter high register 7.1.5 cpu program counter low register 7.2 addressing modes 7.2.1 source immediate the result of an instruction using this addressing mode is placed in the a register, the f register, the sp register, or the x register, which is specified as part of the instruction opcode. operand 1 is an immediate value that serves as a source for the instruction. arithmetic instructions require two sources. instructions using this addressing mode are two bytes in length. examples 7.2.2 source direct the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the inst ruction opcode. operand 1 is an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arithmetic instruct ions require two sources, the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. table 7-4. cpu stack pointer register (cpu_sp) bit # 7 6 5 4 3 2 1 0 field stack pointer [7:0] read/write ???????? default 00000000 bit [7:0]: stack pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack table 7-5. cpu program coun ter high register (cpu_pch) bit # 7 6 5 4 3 2 1 0 field program counter [15:8] read/write ???????? default 00000000 bit [7:0]: program counter [15:8] 8-bit data value holds the higher byte of the program counter table 7-6. cpu program counter low register (cpu_pcl) bit # 7 6 5 4 3 2 1 0 field program counter [7:0] read/write ???????? default 00000000 bit [7:0]: program counter [7:0] 8-bit data value holds the lower byte of the program counter table 7-7. source immediate opcode operand 1 instruction immediate value add a, 7 ;in this case, the immediate value ;of 7 is added with the accumulator, ;and the result is placed in the ;accumulator. mov x, 8 ;in this case, the immediate value ;of 8 is moved to the x register. and f, 9 ;in this case, the immediate value ;of 9 is logically anded with the f ;register and the result is placed ;in the f register. confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 10 of 70 examples : 7.2.3 source indexed the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the instru ction opcode. operand 1 is added to the x register forming an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arit hmetic instructions require two sources, the second source is the a register or x register specified in the opcode. inst ructions using this addressing mode are two bytes. examples 7.2.4 destination direct the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is an address that points to the location of the result. the source for the instruction is either the a register or the x register, which is specif ied as part of the instruction opcode. arithmetic instructi ons require two sources, the second source is the location s pecified by operand 1. instruc- tions using this addressing mode are two bytes in length. examples 7.2.5 destination indexed the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register forming the address that points to the location of the result. the source for the instruction is the a register . arithmetic instructions require two sources, the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are two bytes in length. example 7.2.6 destination direct immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources, the second source is the location specified by operand 1. instructions using this addressing mode are three bytes in length. table 7-8. source direct opcode operand 1 instruction source address add a, [7] ;in this case, the ;value in ;the ram memory location at ;address 7 is added with the ;accumulator, and the result ;is placed in the accumulator. mov x, reg[8] ;in this case, the value in ;the register space at address ;8 is moved to the x register. table 7-9. source indexed opcode operand 1 instruction source index add a, [x+7] ;in this case, the value in ;the memory location at ;address x + 7 is added with ;the accumulator, and the ;result is placed in the ;accumulator. mov x, reg[x+8] ;in this case, the value in ;the register space at ;address x + 8 is moved to ;the x register. table 7-10. destination direct opcode operand 1 instruction destination address add [7], a ;in this case, the value in ;the memory location at ;address 7 is added with the ;accumulator, and the result ;is placed in the memory ;location at address 7. the ;accumulator is unchanged. mov reg[8], a ;in this case, the accumula- ;tor is moved to the regis- ;ter space location at ;address 8. the accumulator ;is unchanged. table 7-11. destination indexed opcode operand 1 instruction destination index add [x+7], a ;in this case, the value in the ;memory location at address x+7 ;is added with the accumulator, ;and the result is placed in ;the memory location at address ;x+7. the accumulator is ;unchanged. table 7-12. destination direct immediate opcode operand 1 operand 2 instruction destination address immediate value confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 11 of 70 examples 7.2.7 destination indexed immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register to form the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources, the second source is the location specified by operand 1 added with the x regi ster. instructions using this addressing mode are three bytes in length. examples 7.2.8 destination direct direct the result of an instruction using this addressing mode is placed within the ram memory. operand 1 is the address of the result. operand 2 is an address that points to a location in the ram memory that is the s ource for the instruction. this addressing mode is only valid on the mov instruction. the instruction using this addressing mode is three bytes in length. example 7.2.9 source indirect post increment the result of an instruction using this addressing mode is placed in the accumulator. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) fo r the source of the instruction. the indirect address is increment ed as part of the instruction execution. this addressing mode is only valid on the mvi instruction. the instruction us ing this addressing mode is two bytes in length. refer to the psoc designer: assembly language user guide for further details on mvi instruction. example 7.2.10 destination indirect post increment the result of an instruction using this addressing mode is placed within the memory sp ace. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. the indirect address is incremented as part of the instruction execution. the sour ce for the instruction is the accumulator. this addressing mode is only valid on the mvi instruction. the instruction us ing this addressing mode is two bytes in length. example add [7], 5 ;in this case, value in the mem- ;ory location at address 7 is ;added to the immediate value of ;5, and the result is placed in ;the memory location at address 7. mov reg[8], 6 ;in this case, the immediate ;value of 6 is moved into the ;register space location at ;address 8. table 7-13. destination indexed immediate opcode operand 1 operand 2 instruction destination index immediate value add [x+7], 5 ;in this case, the value in ;the memory location at ;address x+7 is added with ;the immediate value of 5, ;and the result is placed ;in the memory location at ;address x+7. mov reg[x+8], 6 ;in this case, the immedi- ;ate value of 6 is moved ;into the location in the ;register space at ;address x+8. table 7-14. destination direct direct opcode operand 1 operand 2 instruction destination address source address mov [7], [8] ;in this case, the value in the ;memory location at address 8 is ;moved to the memory location at ;address 7. table 7-15. source indirect post increment opcode operand 1 instruction source address address mvi a, [8] ;in this case, the value in the ;memory location at address 8 is ;an indirect address. the memory ;location pointed to by the indi- ;rect address is moved into the ;accumulator. the indirect ;address is then incremented. table 7-16. destination indirect post increment opcode operand 1 instruction destination address address mvi [8], a ;in this case, the value in ;the memory location at ;address 8 is an indirect ;address. the accumulator is ;moved into the memory loca- ;tion pointed to by the indi- ;rect address. the indirect ;address is then incremented. confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 12 of 70 8.0 instruction set summary the instruction set is summarized in table 8-1 by numerically and serves as a quick refere nce. if more information is needed, the instruction set summary tables are described in detail in the psoc designer assembly language user guide (available on the www. cypress.com web site). table 8-1. instruction set summary sorted numerically by opcode order [1, 2] opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a 03 7 2 add a, [x+expr] c, z 30 9 1 halt 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a 08 4 1 push a 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 14 of 70 9.2 data memory organization the CY7C633XX/638xx/639xx microcontrollers provide up to 256 bytes of data ram. in no rmal usage, the sram is parti- tioned into two areas: stack, and user variables: 9.3 flash this section describes the flash block of the encore ii. much of the user visible flash functionality including programming and security are implemented in the m8c supervisory read only memory (srom). 9.3.1 flash programming and security all flash programming is performed by code in the srom. the registers that control the flas h programming are only visible to the m8c cpu when it is executing out of srom. this makes it impossible to read, write or erase the flash by bypassing the security mechanisms implemented in the srom. customer firmware can only program the flash via srom calls. the data or code images can be sourced via any interface with the appropriate support firmware. this type of programming requires a ?boot-loader? ? a piece of firmware resident on the flash. for safety reasons this boot-loader should not be over written during firmware rewrites. the flash provides four extra au xiliary rows that are used to hold flash block protection flags, boot time calibration values, configuration tables, and any device values. the routines for accessing these auxiliary rows are documented in the srom section. the auxiliary rows are not affected by the device erase function. 9.3.2 in-system programming most designs that include an encore ii part will have a usb connector attached to the usb d+/d- pins on the device. these designs require the ability to program or re-program a part through these two pins alone. the programming protocol is not usb. encore ii devices enable this type of in-system programming by using the d+ and d- pins as the serial programming mode interface. this allows an external controller to cause the encore ii part to enter serial programming mode and then to use the test queue to issue flash access functions in the srom. 9.4 srom the srom holds code that is used to boot the part, calibrate circuitry, and perform flash operations ( ta ble 9-1 lists the srom functions.) the functions of the srom may be accessed in normal user code or operating from flash. the srom exists in a separate me mory space from user code. the srom functions are accessed by executing the super- visory system call instruction (ssc), which has an opcode of 00h. prior to executing the ssc the m8c?s accumulator needs to be loaded with the desired srom function code from table 9-1 . undefined functions will cause a halt if called from user code. the srom functions are executing code with calls; therefore, the functions require stack space. with the exception of reset, all of the srom functions have a parameter block in sram that must be configured before executing the ssc. table 9-2 lists all possible parameter block variables. the meaning of each parameter, with regards to a specific srom function, is described later in this chapter. after reset address 8-bit psp 0x00 stack begins here and grows upward (user can modify) the user determines the amount of memory needed for stack user variables top of ram memory 0xff figure 9-2. data memory organization table 9-1. srom function codes function code function name stack space 00h swbootreset 0 01h readblock 7 02h writeblock 10 03h eraseblock 9 05h eraseall 11 06h tableread 3 07h checksum 3 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 15 of 70 two important variables that are used for all functions are key1 and key2. these variables are used to help discrim- inate between valid sscs and inadvertent sscs. key1 must always have a value of 3ah, while key2 must have the same value as the stack pointer when the srom function begins execution. this would be the stack pointer value when the ssc opcode is executed, plus three. if either of the keys do not match the expected values, the m8c will halt (with the exception of the swbootreset function). the following code puts the correct value in key1 and key2. the c ode starts with a halt, to force the program to jump directly into the setup code and not run into it. halt sscop: mov [key1], 3ah mov x, sp mov a, x add a, 3 mov [key2], a the srom also features return codes and lockouts. 9.4.1 return codes return codes aid in the determination of success or failure of a particular function. the return code is stored in key1?s position in the parameter block. the checksum and tableread functions do not have return codes because key1?s position in the parameter bl ock is used to return other data. read, write, and eras e operations may fail if the target block is read or write protected. bl ock protection levels are set during device programming. the eraseall function overwrites data in addition to leaving the entire user flash in the erase state. the eraseall function loops through the number of flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. after all the user space in all the flash macros are erased, a second loop er ases and then programs each protection block with zeros. 9.5 srom function descriptions 9.5.1 swbootreset function the srom function, swbootrese t, is the function that is responsible for transitioning the device from a reset state to running user code. the swbootreset function is executed whenever the srom is entered with an m8c accumulator value of 00h: the sram parameter block is not used as an input to the function. this will happen, by design, after a hardware reset, because the m8c's accumulator is reset to 00h or when user code execut es the ssc instruction with an accumulator value of 00h. the swbootreset function will not execute when the ssc instruction is executed with a bad key value and a non-zero function code. an encore ii device will execute the halt instruction if a bad value is given for either key1 or key2. the swbootreset function verifies the integrity of the calibration data by way of a 16-bit che cksum, before releasing the m8c to run user code. 9.5.2 readblock function the readblock function is used to read 64 contiguous bytes from flash: a block. the first thing this function does is to check the protection bits and determine if the desired blockid is readable. if read protection is turned on, the read block function will exit setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a read failure. if read protection is not enabled, the function will read 64 bytes from the flash using a romx instruction and store the results in sram using an mvi instruction. the first of the 64 bytes will be stored in sram at the address indicated by the value of the pointer parameter. when the readblo ck completes successfully the accumulator, key1 and key2 wi ll all have a value of 00h. 9.5.3 writeblock function the writeblock function is used to store data in the flash. data is moved 64 bytes at a time from sram to flash using this function. the first thing the writeblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the write- block function will exit setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a write failure. the configuration of the writeblo ck function is straightforward. the blockid of the flash block, where the data is stored, must be determined and stored at sram address fah. table 9-2. srom function parameters variable name sram address key1 / counter / return code 0,f8h key2 / tmp 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch mode 0,fdh delay 0,feh pcl 0,ffh table 9-3. srom return codes return code description 00h success 01h function not allowed due to level of protection on block. 02h software reset without hardware reset. 03h fatal error, srom halted. table 9-4. readblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah flash block number pointer 0,fbh first of 64 addresses in sram where returned data should be stored confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 16 of 70 the sram address of the first of the 64 bytes to be stored in flash must be indicated using the pointer variable in the parameter block (sram address fbh). finally, the clock and delay value must be se t correctly. the clock value determines the length of the wr ite pulse that will be used to store the data in the flash. the clock and delay values are dependent on the cpu speed and must be set correctly. refer to ?clocking? section for additional information. 9.5.4 eraseblock function the eraseblock function is used to erase a block of 64 contiguous bytes in flash. the first thing the eraseblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the eraseblock function will exit setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a write failure. the eraseblock function is only useful as the first step in prog ramming. erasing a block will not cause data in a block to be one hundred percent unreadable. if the objective is to obliterate data in a block, the best method is to perform an eraseblock followed by a writeblock of all zeros. to set up the parameter blo ck for the eraseblock function, correct key values must be stored in key1 and key2. the block number to be erased must be stored in the blockid variable and the clock and delay values must be set based on the current cpu speed. 9.5.5 protectblock function the encore ii devices offer flash protection on a block-by- block basis. ta ble 9-7 lists the protection modes available. in the table, er and ew are used to indicate the ability to perform external reads and writes. for internal writes, iw is used. internal reading is always permitted by way of the romx instruction. the ability to read by way of the srom readblock function is indicated by sr. the protection level is stored in two bits according to ta ble 9-7 . these bits are bit packed into the 64 bytes of the protection bl ock. therefore, each protection block byte stores the protection level for fo ur flash blocks. the bits are packed into a byte, with the lowest numbered block?s protection level stored in the lowest numbered bits table 9-7 . the first address of the protection block contains the protection level for blocks 0 th rough 3; the second address is for blocks 4 through 7. the 64th byte will store the protection level for blocks 252 through 255. the level of protection is only decreased by an eraseall, which places zeros in all locations of the protection block. to set the level of protection, the protectblock function is used. this function takes data from sram, starting at address 80h, and ors it with the current values in the protection block. the result of the or operation is then stored in the protection block. the eraseblock function does not change the protection level for a block. because the sram location for the protection data is fixed and th ere is only one protection block per flash macro, the protectblock function expects very few variables in the parameter block to be set prior to calling the function. the parameter block values that must be set, besides the keys, are the clock and delay values. 9.5.6 eraseall function the eraseall function performs a series of steps that destroy the user data in the flash macr os and resets the protection block in each flash macro to all zeros (the unprotected state). the eraseall function does not affect the three hidden blocks above the protection block, in each flash macro. the first of these four hidden blocks is used to store the protection table for its eight kbytes of user data. the eraseall function begins by erasing the user space of the flash macro with the highest address range. a bulk program of all zeros is then performed on the same flash macro, to table 9-5. writeblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah flash block number (00h?ffh) flash block number (00h?3fh) pointer 0,fbh first of 64 addresses in sram, where the data to be stored in flash is located prior to calling writeblock. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-6. eraseblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah flash block number (00h?7fh) clock 0,fch clock divider used to set the erase pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-7. protection modes mode settings description marketing 00b sr er ew iw unprotected unprotected 01b sr er ew iw read protect factory upgrade 10b sr er ew iw disable external write field upgrade 11b sr er ew iw disable internal write full protection 76543210 block n+3 block n+2 block n+1 block n table 9-8. protectblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 17 of 70 destroy all traces of the previo us contents. the bulk program is followed by a second erase that leaves the flash macro in a state ready for writing. the erase, program, erase sequence is then performed on the next lowest flash macro in the address space if it exists. following the erase of the user space, the protection block for the flash macro with the highest address range is erased. following the erase of the protection block, zeros are written into every bit of the protection table. the next lowest flash macro in the address space then has its protection block erased and filled with zeros. the end result of the eraseall function is that all user data in the flash is destroyed and t he flash is left in an unpro- grammed state, ready to accept one of the various write commands. the protection bits for all user data are also reset to the zero state the parameter block values that must be set, besides the keys, are the clock and delay values. 9.5.7 tableread function the tableread function gives the user access to part-specific data stored in the flash during manufacturing. it also returns a revision id for the die (not to be confused with the silicon id). the table space for the encore ii is simply a 64-byte row broken up into eight tables of eight bytes. the tables are numbered zero through seven. all user and hidden blocks in the cy7c638xx and cy7c639xx parts consist of 64-bytes. an internal table holds the silicon id and returns the revision id. the silicon id is returned in sram, while the revision id is returned in the cpu_a and cpu_x registers. the silicon id is a value placed in the table by programming the flash and is controlled by cypress semiconductor product engineering. the revision id is hard coded into the srom. the revision id is discussed in more detail later in this section. an internal table holds alternate trim values for the device and returns a one-byte internal revision counter. the internal revision counter starts out with a value of zero and is incre- mented each time one of the other revision numbers is not incremented. it is reset to ze ro each time one of the other revision numbers is incremented. the internal revision count is returned in the cpu_a r egister. the cpu_x register will always be set to ffh when trim values are read. the blockid value, in the parameter block, is used to indicate which table should be returned to the user. only the three least significant bits of the blockid parameter are used by tableread function for the cy7c638xx and cy7c639xx. the upper five bits are ignored. when the function is called, it transfers bytes from the table to sram addresses f8h?ffh. the m8c?s a and x registers are used by the tableread function to return the die?s revi sion id. the revision id is a 16-bit value hard coded into the srom that uniquely identifies the die?s design. 9.5.8 checksum function the checksum function calculates a 16-bit checksum over a user specifiable number of blo cks, within a single flash macro (bank) starting from block zero. the blocki d parameter is used to pass in the number of blocks to calculate the checksum over. a blockid val ue of 1 will calculate the checksum of only block 0, wh ile a blockid value of 0 will calculate the checksum of all 256-user blocks. the 16-bit checksum is returned in key1 and key2. the parameter key1 holds the lower eight bi ts of the checksum and the parameter key2 holds the upper eight bits of the checksum. the checksum algorithm executes the following sequence of three instructions over the number of blocks times 64 to be checksumed. romx add [key1], a adc [key2], 0 10.0 clocking the encore ii internal oscillat or outputs two frequencies, the internal 24-mhz oscillator and the 32-khz low-power oscil- lator. the internal 24-mhz oscillator is designed such that it may be trimmed to an output frequency of 24 mhz over temperature and voltage variation. with the presence of usb traffic, the internal 24-mhz oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). without usb traffic, the internal 24-mhz oscillator accuracy is 24 mhz 5% (between 0?70c). no external components are required to achieve this level of accuracy. the internal low-speed oscillator of norminally 32-khz provides a slow clock source for the encore ii in suspend mode, particularly to generate a periodic wake-up interrupt and also to provide a clock to sequential logic during power- up and power-down events when the main clock is stopped. in addition, this oscillator can also be used as a clocking source for the interval timer clock (itmrclk) and capture timer clock (tcapclk). the 32-khz low-power oscillator can table 9-9. eraseall parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. clock 0,fch clock divider us ed to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-10. table read parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah table number to read. table 9-11. checksum parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah number of flash blocks to calculate checksum on. confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 18 of 70 operate in low-power mode or can provide a more accurate clock in normal mode. the internal 32-khz low-power oscil- lator accuracy ranges from ?85% to +120% (between 0?70 c). for applications that require a higher clock accuracy, the cy7c639xx part can optionally be sourced from an external crystal oscillator. when operating in usb mode, the supplied crystal oscillator must be either 12 mhz or 24 mhz in order for the usb blocks to function pr operly. in non-usb mode, the external oscillator can be up to 24 mhz. 10.1 clock architecture description the encore ii clock selection circuitry allows the selection of independent clocks for the cpu, usb, interval timers and capture timers. on the cy7c639xx, the external oscillator can be sourced by the crystal oscillator or when the crystal oscillator is disabled it is sourced directly from the cl kin pin. the external crystal oscillator is fed through the eftb block, which can optionally be bypassed. the cpu clock, cpuclk, can be sourced from the external crystal oscillator or the in ternal 24-mhz oscillator. the selected clock source can optionally be divided by 2 n where n is 0-5,7,8 (see table 10-5 ). usbclk, which must be 12 mhz for the usb sie to function properly, can be sourced by the internal 24-mhz oscillator or the external crystal oscillator. an optional divide by two allows the use of 24-mhz source. the interval timer clock (itmrclk), can be sourced from the external crystal oscillator, the internal 24-mhz oscillator or the internal 32-khz low-power oscillator. a programmable prescaler of 1, 2 or 8 then divides the selected source. the timer capture clock (tcapclk) can be sourced from the external crystal oscillator, internal 24-mhz oscillator, the internal 32-khz low-power oscillator, or from the interval timer clock (itmrclk). when it is not being used by the external crystal oscillator, the clkout pin can be driven from one of many sources. this is used for test and can also be used in some applications. the sources that can drive the clkout are: ? clkin after the optional eftb filter ? internal 24-mhz oscillator ? internal 32-khz low-power oscillator ? cpuclk after the programmable divider 10.1.1 clock control registers 10.1.2 internal clock trim table 10-1. iosc trim (iosctr) [0x34] [r/w] bit # 7 6 5 4 3 2 1 0 field foffset[2:0] gain[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 d d d d d the iosc calibrate register is used to calibrate the internal oscillator. the reset value is undefined but during boot the srom writes a calibration value that is determined during manufacturing test. this va lue should not require change during normal use . this is the meaning of ?d? in the default field bit [7:5]: foffset [2:0] this value is used to trim the frequency of the internal oscilla tor. these bits are not used in factory calibration and will be zero. setting each of these bits causes the appr opriate fine offset in oscillator frequency. foffset bit 0 = 7.5khz foffset bit 1 = 15khz foffset bit 2 = 30khz bit [4:0]: gain [4:0] the effective frequency change of the offset input is controlled through the gain input. a lower value of the gain setting incr eases the gain of the offset input. this value sets the size of ea ch offset step for the internal oscillator. nominal gain change (khz/offsetstep) at each bit, typical conditions (24 mhz operation): gain bit 0 = -1.5khz gain bit 1 = -3.0khz gain bit 2 = -6khz gain bit 3 = -12khz gain bit 4 = -24khz confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 19 of 70 10.1.3 external clock trim 10.1.4 lposc trim table 10-2. xosc trim (xosctr) [0x35] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xosc xgm [2:0] reserved mode read/write ? ? ? r/w r/w r/w ? r/w default 0 0 0 d d d 0 d this register is used to calibrate the external crystal osci llator. the reset value is undefin ed but during boot the srom write s a calibration value that is determined during manufacturing test. th is value should not require change during normal use. this is the meaning of ?d? in the default field bit [7:5]: reserved bit [4:2]: xosc xgm [2:0] amplifier transconductance setting. the xg m settings are recommended for resonators with frequencies of interest for the encore ii as below bit 1: reserved bit 0: mode 0 = oscillator mode 1 = fixed maximum bias test mode resonator xgm setting worst case r (ohms) 6mhz crystal 001 403 12mhz crystal 011 201 24mhz crystal 111 101 6mhz ceramic 001 70.4 12mhz ceramic 011 41 table 10-3. lposc trim (lposctr) [0x36] [r/w] bit # 7 6 5 4 3 2 1 0 field 32-khz low power reserved 32-khz bias trim [1:0] 32-khz freq trim [3:0] read/write r/w ? r/w r/w r/w r/w r/w r/w default d d d d dd d d this register is used to cali brate the 32-khz low-speed oscillator. the reset va lue is undefined but during boot the srom write s a calibration value that is determined during manufacturing test. this value should not require change during normal use. this is the meaning of ?d? in the default field. if the 32-khz low-power bit needs to be written care should be taken not to disturb the 32-khz bias trim and the 32-khz freq trim fields from their factory calibrated values bit 7: 32 khz low power 0 = the 32-khz low-speed oscillator operates in normal mode 1 = the 32-khz low-speed oscillator operates in a low-power mo de. the oscillator continues to function normally but with reduced accuracy bit 6: reserved bit [5:4]: 32-khz bias trim [1:0] these bits control the bias current of the low-power oscillator. 0 0 = mid bias 0 1 = high bias 1 0 = reserved 1 1 = disable (off) important note: do not program the 32-khz bias trim [1:0] field with the reserved 10b value as the oscillator does not oscillate at all corner conditi ons with this setting bit [3:0]: 32-khz freq trim [3:0] these bits are used to trim the frequency of the low-power oscillator confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 20 of 70 10.1.5 cpu/usb clock configuration table 10-4. cpu/usb clock co nfig cpuclkcr) [0x30] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved usb clk /2 disable usb clk select reserved cpuclk select read/write ? r/w r/w ? ? ? ? r/w default 0 0 0 0 0 0 0 0 bit 7: reserved bit 6: usb clk/2 disable this bit only affects the usbclk when the source is the external crystal oscillator. when the usbclk source is the internal 24- mhz oscillator, the divide by two is always enabled 0 = usbclk source is divided by two. this is the correct settin g to use when the internal 24mhz o scillator is used, or when the external source is used with a 24mhz clock 1 = usbclk is undivided. use this se tting only with a 12-mhz external clock bit 5: usb clk select this bit controls the clo ck source for the usb sie 0 = internal 24-mhz oscillator. with the presence of usb traffic, the internal 24-mhz oscillator can be trimmed to meet the usb requirement of 1.5% tolerance (see table 10-6 ) 1 = external clock ? external oscillator on clkin and clkout if the external oscillat or is enabled (the xosc enable bit set in the clkiocr register - table 10-8 ), or the clkin input if the exte rnal oscillator is disabled. internal oscillator is not trimmed to usb traffic. proper usb sie operation requires a 12-mhz or 24-mhz clock accurate to <1.5%. bit [4:1]: reserved bit 0: cpu clk select 0 = internal 24-mhz oscillator. 1 = external crystal oscillator ? external crystal oscillator on clkin and clkout if the external crystal oscillator is enabled , clkin input if the external crystal oscillator is disabled note: the cpu speed selection is config ured using the osc_cr0 register ( table 10-5 ) confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 21 of 70 10.1.6 osc_cr0 clock configuration table 10-5. osc control 0 (osc_cr0) [0x1e0] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved no buzz sleep timer [1:0] cpu speed [2:0] read/write ? ? r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:6]: reserved bit 5: no buzz during sleep (the sleep bit is set in the cpu_scr register? table 11-1 ), the lvd and por detection circuit is turned on periodically to detect any por and lvd events on the vcc pin (the sleep duty cycle bits in the eco_tr are used to control the duty cycle? table 13-3 ). to facilitate the detection of por and lvd event s, the no buzz bit is used to force the lvd and por detection circuit to be continuously enabled during sleep. this results in a faster response to an lvd or por event during slee p at the expense of a slightly hi gher than average sleep current 0 = the lvd and por detection circuit is turned on periodically as configured in the sleep duty cycle 1 = the sleep duty cycle value is overridden. t he lvd and por detection circuit is always enabled note: the periodic sleep duty cycle enabling is independent with the sleep interval shown in the sleep [1:0] bits below bit [4:3]: sleep timer [1:0] note: sleep intervals are approximate bit [2:0]: cpu speed [2:0] the encore ii may operate over a range of cpu clock speeds. the reset value for the cpu speed bits is zero; therefore, the default cpu speed is one- eighth of the internal 24 mhz, or 3 mhz regardless of the cpu speed bit?s setting, if the actual cpu speed is greater than 12 mhz, the 24-mhz operating requirements apply. an example of this scenario is a device that is configur ed to use an external clock, which is supplying a frequency of 2 0 mhz. if the cpu speed register?s value is 0b011, the cpu clock will be 20 mhz. ther efore the supply voltage requirements for the device are the same as if the part was operating at 24 mhz. the operating volt age requirements are not relaxed until the cpu speed is at 12 mhz or less important note: correct usb operations require the cpu clock speed to be at least eight times greater than the usb clock. if the two clocks have the same source then the cpu clock divider should not be set to divide by more than 8. if the two clocks have different sources, care must be taken to ensure that the maximum ratio of usb clock/cpu clock can never exceed 8 across the full specification range of both clock sources sleep timer [1:0] sleep timer clock (in 32khz clock) sleep period (nominal) watchdog period (nominal) 00 64 1.95 msec 6 msec 01 512 15.6 msec 47 msec 10 4096 125 msec 375 msec 11 32768 1 sec 3 sec cpu speed [2:0] cpu when internal oscillator is selected external clock 000 3 mhz (default) clock in / 8 001 6 mhz clock in / 4 010 12 mhz clock in / 2 011 24 mhz clock in / 1 100 1.5 mhz clock in / 16 101 750 khz clock in / 32 110 187 khz clock in / 128 111 reserved reserved confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 22 of 70 10.1.7 usb oscillator lock configuration 10.1.8 timer clock configuration table 10-6. usb osclock clock configuration (osclckcr) [0x39] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved fine tune only usb osclock disable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register is used to trim the internal 24-mhz oscillator using received low-speed usb packets as a timing reference. the usb osclock circuit is active when the internal 24-mhz oscillator provides the usb clock bit [7:2]: reserved bit 1: fine tune only 0 = enable 1 = disable the oscillator lock from perfor ming the course-tune portion of its retuni ng. the oscillator lock must be allowed to perform a course tuning in order to tune the oscillator for corre ct usb sie operation. after the oscillator is properly tuned t his bit can be set to reduce variance in the internal osci llator frequency that would be caused course tuning bit 0: usb osclock disable 0 = enable. with the presence of usb traffic, the inter nal 24-mhz oscillator precisely tunes to 24 mhz 1.5% 1 = disable. the internal 24-mhz oscillator is not trimmed based on usb packets. this setting is useful when the internal oscillator is not sourcing the usbsie clock table 10-7. timer clock config (itmrclkcr) [0x31] [r/w] bit # 7 6 5 4 3 2 1 0 field tcapclk divider tcapclk select itmrclk divider itmrclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 1 1 1 bit [7:6]: tcapclk divider [1:0] tcapclk divider controls the tcapclk divisor 0 0 = divider value 2 0 1 = divider value 4 1 0 = divider value 6 1 1 = divider value 8 bit [5:4]: tcapclk select the tcapclk select field controls the source of the tcapclk 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator ? external crystal oscillator on clkin and clkout if the extern al crystal oscillator is enabl ed, clkin input if the external crystal osc illator is disabled (the xosc enable bit of the clkiocr register is cleared ? ta ble 10 -8 ) 1 0 = internal 32-khz low-power oscillator 1 1 = tcapclk disabled note: the 1024 sec interval timer is based on the assumption that tcapclk is running at 4 mhz. changes in tcapclk frequency will cause a corresponding change in the 1024 sec interval timer frequency bit [3:2]: itmrclk divider itmrclk divider controls the itmrclk divisor. 0 0 = divider value of 1 0 1 = divider value of 2 1 0 = divider value of 3 1 1 = divider value of 4 bit [1:0]: itmrclk select 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator ? external crystal oscillator on clkin and clkout if the extern al crystal oscillator is enabl ed, clkin input if the external crystal oscillator is disabled 1 0 = internal 32-khz low-power oscillator 1 1 = tcapclk confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 23 of 70 10.1.9 clock in / clo ck out configuration 10.2 cpu clock during sleep mode when the cpu enters sleep mo de the cpuclk select (bit 1, table 10-4 ) is forced to the internal oscillator, and the oscil- lator is stopped. when the cpu co mes out of sleep mode it is running on the internal oscillator. the internal oscillator recovery time is three clock cycl es of the internal 32-khz low- power oscillator. if the system requires the cpu to run off the external clock after awaking from sleep mode, firmware will need to switch the clock source for the cpu. if the external clock source is the external oscillator and the osc illator is disabled firmware will need to enable the external oscillator, wait for it to stabilize, and then change the clock source. 11.0 reset the microcontroller supports two types of resets: power on reset (por) and watchdog reset (wdr). when reset is initiated, all registers are restored to their default states and all interrupts are disabled. the occurrence of a reset is recorded in the system status and control register (cpu_scr). bits within this register record the occurrence of por and wdr reset respectively. the firmware can interrogate these bits to determine the cause of a reset. the microcontroller resumes execution from flash address 0x0000 after a reset. the internal clocking mode is active after a reset, until changed by user firmware. note: the cpu clock defaults to 3 mhz (internal 24-mhz oscillator divide-by-8 mode) at por to guarantee operation at the low vcc that might be pr esent during the supply ramp. table 10-8. clock i/o conf ig (clkiocr) [0x32] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xosc select xosc enable eftb disabled clkout select read/write ? ? ? r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:5]: reserved bit 4: xosc select this bit when set, selects the external crys tal oscillator clock as clock source of external clock. care needs to be taken whil e selecting the crystal oscillator clock. first enable the crystal oscillator and wait for few cycles, which is oscillator stabil ization period. then select the crystal clock as clock source. similarly while deselect xt al clock first deselect xtal clock as clock s ource then disable the crystal oscillator. 0 = not select external crystal oscillator clock 1 = select the external crystal oscillator clock bit 3: xosc enable this bit when set enables the external crystal oscillator. the ex ternal crystal oscillator shares pads clkin and clkout with two gpios ? p0.0 and p0.1, respectively. when the external cryst al oscillator is enabled, the clkin signal comes from the external crystal oscillator block and the output enables on the gpios for p0.0 and p0.1 are disabled, eliminating the possibili ty of contention. when the external crystal oscillator is disabl ed the source for clkin signal comes from the p0.0 gpio input. 0 = disable the external oscillator 1 = enable the external oscillator note: the external crystal oscillator startup time takes up to 2 ms. bit 2: eftb disabled this bit is only available on the cy7c639xx 0 = enable the eftb filter 1 = disable the eftb filter, causi ng clkin to bypass the eftb filter bit [1:0]: clkout select 0 0 = internal 24-mhz oscillator 0 1 = external crystal oscillator ? external crystal oscillator on clkin and clkout if the extern al crystal oscillator is enabl ed, clkin input if the external oscillator is disabled 1 0 = internal 32-khz low-power oscillator 1 1 = cpuclk confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 24 of 70 11.1 power-on reset por occurs every time the power to the device is switched on. por is released when the supply is typically 2.6v for the upward supply transition, with typically 50 mv of hysterisis during the power on transient. bit 4 of the system status and control register (cpu_scr) is set to record this event (the register contents are set to 00010000 by the por). after a por, the microprocessor is held off for approximately 20 ms for the vcc supply to stabilize before executing the first instruction at address 0x00 in the flash. if the vcc voltage drops below the por downward supply trip point, por is reasserted. the vcc supply needs to ramp linearly from 0 to 4v in 0 to 200 ms. important : the pors status bit is set at por and can only be cleared by the user, and cannot be set by firmware. 11.2 watchdog timer reset the user has the option to enable the wdt. the wdt is enabled by clearing the pors bit. once the pors bit is cleared, the wdt cannot be disabled. the only exception to this is if a por event takes place, which will disable the wdt. the sleep timer is used to generate the sleep time period and the watchdog time period. the sleep timer uses the internal 32-khz low-power oscillator system clock to produce the sleep time period. the user can program the sleep time period using the sleep timer bits of the osc_cr0 register ( table 10-5 ). when the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer interrupt vector will be generated. the watchdog timer period is automatically set to be three counts of the sleep timer overflows. this represents between two and three sleep intervals depending on the count in the sleep timer at the previous wdt clear. when this timer reaches three, a wdr is generated. the user can either clear the wdt, or the wdt and the sleep timer. whenever the user writ es to the reset wdt register (res_wdt), the wdt will be cleared. if the data that is written is the hex value 0x38, the sleep timer will also be cleared at the same time. note: 3. c = clear. this bit can only be cleared by the user and cannot be set by firmware. table 11-1. system status and control register (cpu_scr) [0xff] [r/w] bit # 7 6 5 4 3 2 1 0 field gies reserved wdrs pors sleep reserved reserved stop read/write r ? r/c [3] r/c [3] r/w ? ? r/w default 0 0 0 1 00 0 0 the bits of the cpu_scr register are used to convey status and control of events for various functions of an encore ii device bit 7: gies the global interrupt enable status bit is a read only status bit and its use is discouraged. the gies bit is a legacy bit, whic h was used to provide the ability to read the gie bit of the cpu_ f register. however, the cpu_f register is now readable. when this bit is set, it indicates that the gie bit in the cpu_f regi ster is also set which, in turn, indicates that the microproces sor will service interrupts 0 = global interrupts disabled 1 = global interrupt enabled bit 6: reserved bit 5: wdrs the wdrs bit is set by the cpu to indicate that a wdr event ha s occurred. the user can read th is bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no wdr 1 = a wdr event has occurred bit 4: pors the pors bit is set by the cpu to indica te that a por event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no por 1 = a por event has occurred. (note that wdr events will not occur until this bit is cleared) bit 3: sleep set by the user to enable cpu sleep state. cpu will remain in sleep mode until any interrupt is pending. the sleep bit is cover ed in more detail in the sleep mode section 0 = normal operation 1 = sleep bit [2:1]: reserved bit 0: stop this bit is set by the user to halt the cpu. the cpu will remain halted until a reset (wdr, por, or external reset) has taken place. if an application wants to stop code execution until a re set, the preferred method would be to use the halt instruction rather than writing to this bit 0 = normal cpu operation 1 = cpu is halted (not recommended) confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 25 of 70 12.0 sleep mode the cpu can only be put to sleep by the firmware. this is accomplished by setting the sleep bit in the system status and control register (cpu_scr). this stops the cpu from executing instructions, and the cpu will remain asleep until an interrupt comes pending, or there is a reset event (either a power on reset, or a watchdog timer reset). the low-voltage detector circuit (lvd) drops into fully functional power-reduced states , and the laten cy for the lvd is increased. the actual latency can be traded against power consumption by changing sleep duty cycle field of the eco_tr register. the internal 32-khz low-speed oscillator remains running. prior to entering suspend mode, firmware can optionally configure the 32-khz low-speed oscillator to operate in a low- power mode to help reduce the over all power consumption (using bit 7, table 10-3 ). this will help save approximately 5 ua; however, the trade off is that the 32-khz low-speed oscillator will be less accurate (?85% to +120% deviation). all interrupts remain active. only the occurrence of an interrupt will wake the part from sleep. the stop bit in the system status and control register (cpu_scr) must be cleared for a part to resume out of sleep. the global interrupt enable bit of the cpu flags register (cpu_f) does not need to be set. any unmasked interrupt will wake t he system up. it is optional. when the cpu enters sleep mode the cpuclk select (bit 1, table 10-4 ) is forced to the internal oscillator. the internal oscillator recovery time is th ree clock cycles of the internal 32-khz low-power oscillator. the internal 24-mhz oscillator restarts immediately on exiting sleep mode. if the external crystal oscillator is used, firmware will need to switch the clock source for the cpu. unlike the internal 24-mhz oscillator, the external oscillator is not automatically shut-down dur ing sleep. systems that need the external oscillator disabled in sleep mode will need to disable the external oscillator prior to entering sleep mode. in systems where the cpu runs off the external oscillator firmware will need to switch the cpu to the internal oscillator prior to disabling the external oscillator. on exiting sleep mode, once the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). the sleep interrupt allows the microcontroller to wake up periodically and poll system co mponents while maintaining very low average power consumption. the sleep interrupt may also be used to provide periodic interrupts during non- sleep modes. table 11-2. reset watchdog timer (reswdt) [0xe3] [w] bit # 7 6 5 4 3 2 1 0 field reset watchdog timer [7:0] read/write w w w w ww w w default 0 0 0 0 00 0 0 any write to this register will clear watchdog time r, a write of 0x38 will also clear the sleep timer bit [7:0]: reset watchdog timer [7:0] confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 26 of 70 13.0 low-voltage detect control 13.0.1 por compare state table 13-1. low-voltage control register (lvdcr) [0x1e3] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved porlev[1:0] reserved vm[3:0] read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the configuration of the power-on reset / low-voltage-detect block bit [7:6]: reserved bit [5:4]: porlev[1:0] this field controls the level below which the precis ion power-on-reset (ppor) detector generates a reset 0 0 = 2.7v range (trip near 2.6v) 0 1 = 3v range (trip near 2.9v) 1 0 = 5v range, > 4.75v (trip near 4.65v) 1 1 = ppor will not generate a reset, but values read from the voltage monitor comparators register ( table 13-2 ) give the internal ppor comparator state with trip point set to the 3v range setting bit 3: reserved bit [2:0]: vm[2:0] this field controls the level below which the low-voltage-detect trips ? possibly generating an interrupt and the level at whic h the flash is enabled for operation. vm[2:0] lvd trip point (v) min. max. 000 2.892 2.950 001 2.991 3.053 010 3.102 3.164 011 2.627 2.680 100 4.439 4.528 101 4.597 4.689 110 4.680 4.774 111 4.766 4.862 table 13-2. voltage monitor comparators register (vltcmp) [0x1e4] [r] bit # 7 6 5 4 3 2 1 0 field reserved lvd ppor read/write ? ? ? ? ?? r r default 0 0 0 0 00 0 0 this read-only register allows reading t he current state of the low- voltage-detect and precision- power-on-reset comparators bit [7:2]: reserved bit 1: lvd this bit is set to indicate that the low-voltage-detect compar ator has tripped, indicating that the supply voltage is below the trip point set by vm[2:0] (see table 13-1 ) 0 = no low-voltage-detect event 1= a low-voltage-detect has tripped bit 0: ppor this bit is set to indicate that the prec ision-power-on-reset comparator has tripped, indicating that the supply voltage is bel ow the trip point set by porlev[1:0] 0 = no precision-power-on-reset event 1= a precision-power-on-reset event has tripped confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 27 of 70 13.0.2 eco trim register 14.0 general purpose i/o ports 14.1 port data registers 14.1.1 p0 data table 13-3. eco (eco_tr) [0x1eb] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep duty cycle [1:0] reserved read/write r/w r/w ? ? ? ? ? ? default 0 0 0 0 00 0 0 this register controls the ratios (in numbers of 32-khz clock pe riods) of ?on? time versus ?off ? time for lvd and por detection circuit bit [7:5]: sleep duty cycle [1:0] 0 0 = 128 periods of the internal 32-khz low-speed oscillator 0 1 = 512 periods of the internal 32-khz low-speed oscillator 1 0 = 32 periods of the internal 32-khz low-speed oscillator 1 1 = 8 periods of the internal 32-khz low-speed oscillator table 14-1. p0 data register (p0data)[0x00] [r/w] bit # 7 6 5 4 3 2 1 0 field p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/clkout p0.0/clkin read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register contains the data for port 0. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the cu rrent state of the port 0 pins. bit 7: p0.7 data p0.7 only exists in the cy7c638xx and cy7c639xx bit [6:5]: p0.6 ? p0.5 data / tio1 and tio0 beside their use as the p0.6 ? p0.5 gpios, these pins can also be used for the alternate functions as the capture timer input or timer output pins (tio1 and tio0). to configure the p0.5 and p0.6 pins, refer to the p0.5/tio0 ? p0.6/tio1 configuration register ( table 14-9 ) the use of the pins as the p0.6 ? p0.5 gpios and the alternate functions exist in all the encore ii parts bit [4:2]: p0.4 ? p0.2 data / int2 ? int0 beside their use as the p0.4 ? p0.2 gpios, these pins can al so be used for the alternate functions as the interrupt pins (int0 ? int2). to configure the p0.4 ? p0.2 pins, refer to the p0.2/int0 ? p0.4/int2 configuration register ( table 14-8 ) the use of the pins as the p0.4 ? p0.2 gpios and the alternate functions exist in all the encore ii parts bit 1: p0.1 / clkout beside its use as the p0.1 gpio, this pin can also be used for the alternate function as the cl k out pin. to configure the p0.1 pin, refer to the p0.1/clkout configuration register ( table 14-7 ) bit 0: p0.0 / clkin beside its use as the p0.0 gpio, this pin can also be used for the alternate function as the cl kin pin. to configure the p0.0 pin, refer to the p0.0/clkin configuration register ( table 14-6 ) confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 28 of 70 14.1.2 p1 data 14.1.3 p2 data 14.1.4 p3 data table 14-2. p1 data regist er (p1data) [0x01] [r/w] bit # 7 6 5 4 3 2 1 0 field p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d- p1.0/d+ read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 1. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the cu rrent state of the port 1 pins. bit 7: p1.7 data p1.7 only exists in the cy7c638xx and cy7c639xx bit [6:3]: p1.6 ? p1.3 data / spi pi ns (smiso, smosi, sclk, ssel) beside their use as the p1.6 ? p1.3 gpios, these pins can also be used for the alternate func tion as the spi interface pins. to configure the p1.6 ? p1.3 pi ns, refer to the p1.3 ? p1.6 configuration register ( table 14-14 ) the use of the pins as the p1.6 ? p1.3 gpios and the alternate functions exist in all the encore ii parts. bit 2: p1.2 / vreg on the cy7c639xx, this pin can be used as the p1.2 gpio or the vreg output. if the vr eg output is enabled (bit 0 ta ble 19 -1 is set), a 3.3v source is placed on the pin and the gpio function of the pin is disabled on the cy7c638xx and cy7c63310, this pin can only be used as the vreg output when usb mode is enabled. in non-usb mode, this pin can be used as the p1.2 gpio bit [1:0]: p1.1 ? p1.0 / d- and d+ when usb mode is disabled (bit 7 in table 21-1 is clear), the p1.1 and p1.0 bits are used to control the state of the p1.0 and p1.1 pins. when the usb mode is enabled, the p1.1 and p1.0 pins are used as the d- and d+ pins respectively. if the usb force state bit (bit 0 in ta ble 18 -1 ) is set, the state of the d- and d+ pins can be controlled by writing to the d- and d+ bits table 14-3. p2 data regist er (p2data) [0x02] [r/w] bit # 7 6 5 4 3 2 1 0 field p2.7 ? p2.2 p2.1 ? p2.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 2. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 2 pins bit [7:2]: p2 data [7:2] p2.7 ? p2.2 only exis t in the cy7c639xx. note that the cy7c63903-pvxc (28 pin ssop package) only has p2.7 - p2.4 bit [1:0]: p2 data [1:0] p2.1 ? p2.0 only exist in the cy7c63823 and cy7c639xx (except the cy7c63903-pvxc 28 pin ssop package) table 14-4. p3 data regist er (p3data) [0x03] [r/w] bit # 7 6 5 4 3 2 1 0 field p3.7 ? p3.2 p3.1? p3.0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 3. writing to this regi ster sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 3 pins bit [7:2]: p3 data [7:2] p3.7 ? p3.2 only exist in the cy7c 639xx. note that the cy 7c63903-pvxc 28 pin ssop package only has p3.7?p3.4 bit [1:0]: p3 data [1:0] p3.1 ? p3.0 only exist in the cy7c63823 and cy7c639xx (except the cy7c63903-pvxc 28 pin ssop package) confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 29 of 70 14.1.5 p4 data 14.2 gpio port configuration all the gpio configuration registers have common configu- ration controls. the following is the bit definitions of the gpio configuration registers 14.2.1 int enable when set, the int enable bit allows the gpio to generate inter- rupts. interrupt generate can occur regardless of whether the pin is configured for input or output. all interrupts are edge sensitive, however for any interr upt that is shared by multiple sources (ie. ports 2,3 and 4) all inputs must be de-asserted before a new interrupt can occur. when clear, the corresponding interrupt is disabled on the pin. it is possible to configure gpios as outputs, enable the interrupt on the pin and then to generate the interrupt by driving the appropriate pin state. this is useful in test and may find value in applications as well. 14.2.2 int act low when set, the corresponding interrupt is active on the falling edge. when clear, the corresponding interrupt is active on the rising edge. 14.2.3 ttl thresh when set, the input has ttl threshold. when clear, the input has standard cmos threshold. 14.2.4 high sink when set, the output can sink up to 50 ma. when clear, the output can sink up to 8 ma. on the cy7c639xx, only the p3.7, p2.7, p0.1, and p0.0 have 50ma sink drive capability. other pins have 8ma sink drive capability. on the cy7c638xx, only the p1.7?p1.3 have 50-ma sink drive capability. other pins have 8ma sink drive capability. 14.2.5 open drain when set, the output on the pin is determined by the port data register. if the corresponding bit in the port data register is set, the pin is in high impedanc e state. if the corresponding bit in the port data register is clear, the pin is driven low. when clear, the output is driven low or high. 14.2.6 pull-up enable when set the pin has a 7k pull-up to vdd (or vreg for ports with v3.3 enabled). when clear, the pull-up is disabled. 14.2.7 output enable when set, the output driv er of the pin is enabled. when clear, the output driver of the pin is disabled. for pins with shared functions there are some special cases. p0.0(clkin) and p0.1(clkout) can not be output enabled when the crystal oscillator is en abled. output enables for these pins are overridden by xosc enable. p1.2(vreg), p1.3(ssel), p1.4(sclk), p1.5(smosi) and p1.6(smiso) can be used for their dedicated functions or for gpio. to enable the pin for gpio use clear the corresponding spi use bit or the output enable will have no effect. 14.2.8 vreg output / spi use the p1.2(vreg), p1.3(ssel) , p1.4(sclk), p1.5(smosi) and p1.6(smiso) pins can be used for their dedicated functions or for gpio. to enable the pin for gpio, clear the corresponding vreg output or spi use bit. the spi function controls the output enable for it s dedicated function pins when their gpio enable bit is clear 14.2.9 3.3v drive the p1.3(ssel), p1.4(s clk), p1.5(smosi) and p1.6(smiso) pins have an alternate voltage source from the voltage regulator. if the 3.3v drive bit is set a high level is driven from the voltage regulator instead of from vdd. setting the 3.3v drive bit does not enable the voltage regulator. that must be done explicitly by settin g the vreg enable bit in the vregcr register ( table 19-1 ). table 14-5. p4 data regist er (p4data) [0x04] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p4.3 ? p4.0 read/write r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 4. writing to this register sets the bit valu es to be output on output-enabled pins. r eading from this register returns the current state of the port 2 pins bit [7:4]: reserved bit [3:0]: p4 data [3:0] p4.3 ? p4.0 only exist in the cy7c639xx except the cy7c63903-pvxc confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 30 of 70 14.2.10 p0.0/clkin configuration 14.2.11 p0.1/clkout configuration figure 14-1. block diagram of a gpio (tbd) table 14-6. p0.0/clkin conf iguration (p00cr) [0x05] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write -- r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this pin is shared between the p0.0 gpio use and the clkin pin for the external crys tal oscillator. when the external oscillato r is enabled the settings of this register are ignored the use of the pin as the p0.0 gpio is available in all the encor e ii parts. the alternate functi on of the pin as the clkin is only available in the cy7c639xx. when the external oscillator is e nabled (the xosc enable bit of the clkiocr register is set - ta ble 10 -8 ), the gpio function of the pin is disabled table 14-7. p0.1/clkout configuration (p01cr) [0x06] r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this pin is shared between the p0.1 gpio use and the clkout pi n for the external crystal oscillator. when the external oscillat or is enabled the settings of this register are ignored. when clk ou tput is set , the internally se lected clock is sent out onto p0.1clkout pin. the use of the pin as the p0.1 gpio is available in all the enco re ii parts. the alternate functi on of the pin as the clkout is only available in the cy7c639xx. when the external oscillator is enabled (the xosc enable bit of the clkiocr register is set - table 10-8 ), the gpio function of the pin is disabled high sink for this pin is available only on the cy7c639xx bit 7: clk output 0 = the clock output is disabled 1 = the clock selected by the clk select field (bit [1:0] of the clkiocr register ? table 10-8 ) is driven out to the pin confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 31 of 70 14.2.12 p0.2/int0 ? p0 .4/int2 configuration 14.2.13 p0.5/tio0 ? p0.6/tio1 configuration 14.2.14 p0.7 configuration table 14-8. p0.2/int0 ? p0.4/int2 config uration (p02cr ? p04cr) [0x07 ? 0x09] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int act low ttl thresh reserved open drain pull-up enable output enable read/write ? ? r/w r/w ? r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the opera tion of pins p0.2?p0.4 respectively. these pi ns are shared between the p0.2?p0.4 gpios and the int0 ? int2. these registers exist in all encore ii parts. the int0?int2 interrupts are different than all the other gpio interrupts. these pins are connected direct ly to the interrupt controller to provi de three edge sensitive interrupts with indep endent interrupt vectors. these interrupts occur on a rising edge when int act low is clear and on a falling edge when int act low is set. these pins are enabled as interrupt source s in the interrupt controller registers ( table 17-8 and ta ble 17 -6 ). to use these pins as interrupt inputs conf igure them as inputs by clearing the corresp onding output enable. if the int0 ? int2 pins are configured as outputs with inte rrupts enabled, firmware can generate an inte rrupt by writing the appropriate value to the p0.2, p0.3 and p0.4 data bits in the p0 data register regardless of whether the pins are used as interrupt or gpio pins the int enable, int act low, ttl threshold, high sink, open drain, and pull-up enable bits control the behavior of the pin the p0.2/int0?p0.4/int2 pins are indivi dually configured with the p02cr (0x07), p 03cr (0x08), and p04cr (0x09) respec- tively. note: changing the state of the int act low bit can cause an unint entional interrupt to be generated. when configuring these interrupt sources, it is best to follow the following procedure: 1. disable interrupt source 2. configure interrupt source 3. clear any pending interrupts from the source 4. enable interrupt source table 14-9. p0.5/tio0 ? p0.6/tio1 configuration (p05cr ? p06cr) [0x0a ? 0x0b] [r/w] bit # 7 6 5 4 3 2 1 0 field tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p0.5 through p0.6 , respectively. these registers exist in all encore ii parts. p0.5 and p0.6 are shared with tio0 and tio1, respectively. to use these pins as capture timer inputs, configure them as inputs by clearing the corresponding output enable. to use tio0 and ti o1 as timer outputs, set the tiox output and output enable bits. if these pins are configured as outputs and the tio outp ut bit is clear, firmware can control the tio0 and tio1 inputs by writing the value to the p0.5 and p0.6 data bits in the p0 data register regardless of whether either pin is used as a tio or gpio pin the int enable, int act low, ttl threshold, high sink, open drain , and pull-up enable control the behavior of the pin. tio0(p0.5) when enabled outputs a positive pulse from the 1024us inte rval timer. this is the same signal that is used internall y to generate the 1024us timer interrupt. this signal is not gated by the interrupt enable state. tio1(p0.6) when enabled outputs a positive pulse from the progra mmable interval timer. this is the same signal that is used internally to generate the programmable timer interval interr upt. this signal is not gated by the interrupt enable state the p0.5/tio0 and p0.6/tio1 pins are individually configur ed with the p05cr (0x0a) and p06cr (0x0b), respectively table 14-10. p0.7 configuration (p07cr) [0x0c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the operation of pin p0.7. the p0.7 pin only exists in the cy7c638xx and cy7c639xx confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 32 of 70 14.2.15 p1.0/d- configuration 14.2.16 p1.1/d- configuration 14.2.17 p1.2 configuration 14.2.18 p1.3 conf iguration (ssel) table 14-11. p1.0/d- config uration (p10cr) [0x0d] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved ps/2 pull-up enable output enable read/write r/w r/w r/w ? ?? r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.0 (d+) pin wh en the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 21-1 for information on enabling usb. when usb is enabled, none of t he controls in this register have any affect on the p1.0 pin. note : the p1.0 is an open drain only output. it can actively dr ive a signal low, but cannot actively drive a signal high. bit 1: ps/2 pull-up enable 0 = disable the 5k-ohm pull-up resistors 1 = enable 5k-ohm pull-up resistors for both p1.0 and p1.1. enable the use of the p1.0 (d+) and p1.1 (d-) pins as a ps2 style interface table 14-12. p1.1/d+ configuration (p11cr) [0x0e] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low res erved open drain reserved output enable read/write ? r/w r/w ? ? r/w ? r/w default 0 0 0 0 00 0 0 this register controls the oper ation of the p1.1 (d-) pin when the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 21-1 for information on enabling usb. when usb is enabled, none of the controls in this register have any affect on the p1.1 pin. when usb is disabled , the 5kohm pull-up resistor on th is pin can be enabled by the ps/2 pull-up enable bit of the p10cr register ( table 14-11 ) table 14-13. p1.2 configuration (p12cr) [0x0f] [r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl thresh old reserved open drain pullup enable output enable read/write r/w r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.2 bit 7: clk output 0 = the internally selected clock is not sent out onto p1.2 pin 1 = this clk output is used to observe connected external cryst al oscillator clock connected in cy7c639xx. when clk output is set, the internally selected clock is sent out onto p1.2 pin table 14-14. p1.3 configuration (p13cr) [0x10] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.3 pin. this register exists in all encore ii parts the p1.3 gpio?s threshold is always set to ttl when the spi hardware is enabled, the output enable and output stat e of the pin is controlled by the spi circuitry. when the sp i hardware is disabled, the pin is controlle d by the output enable bit and the corresponding bit in the p1 data register. regardless of whether the pin is used as an spi or gpio pin the int enable, int act low, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin high sink for this pin is available only on the cy7c638xx confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 33 of 70 14.2.19 p1.4 ? p1.6 configurat ion (sclk, smosi, smiso) 14.2.20 p1.7 configuration 14.2.21 p2 configuration 14.2.22 p3 configuration table 14-15. p1.4 ? p1.6 configuration (p14cr ? p16cr) [0x11 ? 0x13] [r/w] bit # 7 6 5 4 3 2 1 0 field spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p1.4?p1.6, respectively. these re gisters exist in all encore ii parts the p1.4?p1.6 gpio?s threshold is always set to ttl when the spi hardware is enabled, pins t hat are configured as spi use have their output enable and output state controlled by the spi circuitry. when the spi hardware is disabled or a pin has its spi use bit clear, the pin is controlled by the output en able bit and the corresponding bit in the p1 data register. regardless of whether any pin is used as an spi or gpio pin the int enable, int act low, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin high sink for these pins is available only on the cy7c638xx bit 7: spi use 0 = disable the spi alternate function. the pin is used as a gpio 1 = enable the spi function. the spi circ uitry controls the output of the pin important note for comm mode s 01 or 10 (spi master or spi slave, see table 15-2): when configured for spi (spi use = 1 and comm modes [1:0] = spi master or spi slave mode), the input/output direction of pins p1.3, p1.5, and p1.6 is set automatically by the spi logic. however, pin p1.4's input/outpu t direction is not automaticall y set; it must be explicitly set by firmware . for spi master mode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input. table 14-16. p1.7 configuration (p17cr) [0x14] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 this register controls the operation of pin p1.7. th is register only exists in cy7c638xx and cy7c639xx high sink for this pin is available only on the cy7c638xx table 14-17. p2 configuration (p2cr) [0x15] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register only exists in cy7c638xx an d cy7c639xx. in cy7c638xx this register co ntrols the operation of pins p2.0?p2.1. in the cy7c639xx, this register contro ls the operation of pins p2.0?p2.7 high sink is only available on pin p2.7 and only on the cy7c639xx table 14-18. p3 configuration (p3cr) [0x16] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 this register exists in cy7c638xx and cy7c639xx. in cy7c638xx th is register controls the operat ion of pins p3.0?p3.1. in the cy7c639xx, this register controls the operation of pins p3.0?p3.7 high sink is only available on pin p3.7 and only on the cy7c639xx confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 34 of 70 14.2.23 p4 configuration 15.0 serial peripheral interface (spi) the spi master/slave interface core logic runs on the spi clock domain, making its f unctionality independent of system clock speed. spi is a four pin serial interface comprised of a clock, an enable and two data pins. 15.1 spi data register when an interrupt occurs to indicate to firmware that an byte of receive data is available, or the transmitter holding register is empty, firmware has 7 spi clocks to manage the buffers ? to empty the receiver buffer, or to refill the transmit holding register. failure to meet this timing requirement will result in incorrect data transfer. table 14-19. p4 configuration (p4cr) [0x17] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w- r/w default 0 0 0 0 0 0 0 0 this register exists only in the cy7c639xx. this register controls the operation of pins p4.0?p4.3 table 15-1. spi data register (spidata) [0x3c] [r/w] bit # 7 6 5 4 3 2 1 0 field spidata[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when read, this register returns the cont ents of the receive buffer. when written, it loads the transmit holding register bit [7:0]: spi data [7:0] confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 35 of 70 15.2 spi configure register table 15-2. spi configure register (spicr) [0x3d] [r/w] bit # 7 6 5 4 3 2 1 0 field swap lsb first comm mode cpol cpha sclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: swap 0 = swap function disabled 1 = the spi block swaps its use of smosi and smiso. among other things, this can be useful in implementing single wire spi- like communications bit 6: lsb first 0 = the spi transmits and receives th e msb (most significant bit) first 1 = the spi transmits and receives the lsb (least significant bit) first. bit [5:4]: comm mode [1:0] 0 0: all spi communication disabled 0 1: spi master mode 1 0: spi slave mode 1 1: reserved bit 3: cpol this bit controls the spi clock (sclk) idle polarity 0 = sclk idles low 1 = sclk idles high bit 2: cpha the clock phase bit controls the phase of the clock on which data is sampled. ta ble 15 -3 below shows the timing for the various combinations of lsb first, cpol, and cpha bit [1:0]: sclk select this field selects the speed of the master sclk. when in master mode, sclk is genera ted by dividing the base cpuclk important note for comm modes 01b or 10b (spi master or spi slave): when configured for spi, (spi use = 1 ? table 14-15 ), the input/output direction of pins p1.3, p1.5, and p1.6 is set automati- cally by the spi logic. however, pin p1.4's input/output direction is not automaticall y set; it must be explicitly set by firmw are. for spi master mode, pin p1.4 must be configured as an outpu t; for spi slave mode, pin p1.4 must be configured as an input. confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 36 of 70 table 15-3. spi mode timing vs lsb first, cpol and cpha lsb first cpha cpol diagram 00 0 001 010 011 100 101 110 111 sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x msb x bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 37 of 70 15.3 spi interface pins the spi interface uses the p1.3 ? p1.6 pins. these pins are configured using the p1.3 and p1.4-p1.6 configuration. 16.0 timer registers all timer functions of the encore ii are provided by a single timer block. the timer block is asynchronous from the cpu clock. 16.1 registers 16.1.1 free running timer low order byte 16.1.2 free running timer high order byte table 15-4. spi sclk frequency sclk select cpuclk divisor sclk frequency when cpuclk = 12 mhz 24 mhz 00 6 2mhz 4mhz 01 12 1mhz 2mhz 10 48 250khz 500khz 11 96 125khz 250khz table 15-4. spi sclk frequency table 16-1. free running timer low order byte (frtmrl) [0x20] [r/w] bit # 7 6 5 4 3 2 1 0 field free running timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: free running timer [7:0] this register holds the low order byte of the 16-bit free-running timer. reading this register causes the high order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously. for reads the actual read occurs in the cycle when the low order is read. for writes th e actual time the write occurs is the cy cle when the high order is written. when reading the free running timer, the low order byte should be read first and the high order second. when writing, high order byte should be written first then low order byte table 16-2. free running timer high order byte (frtmrh) [0x21] [r/w] bit # 7 6 5 4 3 2 1 0 field free running timer [15:8] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: free running timer [15:8] when reading the free running timer, the low order byte should be read first and the high order second. when writing, high order byte should be written first then low order byte confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 38 of 70 16.1.3 timer capture 0 rising 16.1.4 capture 1 rising 16.1.5 timer capture 0 falling 16.1.6 timer capture 1 falling table 16-3. timer capture 0 rising (tcap0r) [0x22] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 rising [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 0 rising [7:0] this register holds the value of the free running timer when the last rising edge occurred on the tcap0 input. when capture 0 is in 8-bit mode, the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. wh en capture 0 is in 16-bit mode this register ho lds the lower order 8 bits of the 16-bit timer table 16-4. timer capture 1 rising (tcap1r) [0x23] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 rising [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 1 rising [7:0] this register holds the value of the free running timer when the last rising edge occurred on the tcap1 input. the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode t his register holds the high order 8 bits of th e 16-bit timer from the last capture 0 risi ng edge. when capture 0 is in 16-bit mode this register will be loaded with high order 8 bi ts of the 16-bit timer on tcap0 rising edge table 16-5. timer capture 0 falling (tcap0f) [0x24] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 falling [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 0 falling [7:0] this register holds the value of the free running timer when the last falling edge occurred on the tcap0 input. when capture 0 is in 8-bit mode, the bits that are stor ed here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode this register ho lds the lower order 8 bits of the 16-bit timer table 16-6. timer capture 1 falling (tcap1f) [0x25] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 falling [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 1falling [7:0] this register holds the value of the free running timer when th e last falling edge occurred on the tcap1 input. the bits that are stored here are selected by the prescale [2:0] bits in the ti mer configuration register. when capture 0 is in 16-bit mode t his register holds the high order 8 bits of t he 16-bit timer from the last capture 0 falling edge. when capture 0 is in 16-bit mode this register will be loaded with high order 8 bi ts of the 16-bit timer on tcap0 falling edge confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 39 of 70 16.1.7 programmable interval low byte 16.1.8 programmable interval high byte 16.1.9 programmable interval reload low byte 16.1.10 programmable interval reload high byte table 16-7. programmable interval timer low (pitmrl) [0x26] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: prog interval timer [7:0] this register holds the low order byte of the 12-bit programmable interval timer. read ing this register causes the high order b yte to be moved into a holding register allowing an automatic read of all 12 bits simultaneously table 16-8. programmable interval timer high (pitmrh) [0x27] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer [11:8] read/write -- -- -- -- r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit [3:0]: prog internal timer [11:8] this register holds the high order nibble of the 12-bit programm able interval timer. reading this register returns the high ord er nibble of the 12-bit timer at the instant that the low order byte was last read table 16-9. programmable interval reload low (pirl) [0x28] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: prog interval [7:0] this register holds the lower 8 bits of the timer. while writ ing into the 12-bit reload register, write the higher nibble first then lower byte table 16-10. programmable interval reload high (pirh) [0x29] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval[11:8] read/write -- -- -- -- r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit [3:0]: prog interval [11:8] this register holds the higher 4 bits of the timer. while writ ing into the 12-bit reload register, write the higher nibble firs t then lower byte confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 40 of 70 16.1.11 timer configuration 16.1.12 capture interrupt enable table 16-11. timer configuration (tmrcr) [0x2a] [r/w] bit # 7 6 5 4 3 2 1 0 field first edge hold 8-bit capture prescale [2:0] cap0 16bit enable reserved read/write r/w r/w r/w r/w r/w ? ? ? default 0 0 0 0 00 0 0 bit 7: first edge hold the first edge hold function applies to all four-capture timers. 0 = the time of the most recent edge is held in the capture ti mer data register. if multiple edges have occurred since reading the capture timer, the time for the most recent one will be read 1 = the time of the first occurrence of an edge is held in the capture timer data register unt il the data is read. subsequent edges are ignored until the capture timer data register is read. bit [6:4]: 8-bit capture prescale [2:0] this field controls which 8 bits of the 16 free running timer are captured when in bit mode 0 0 0 = capture timer[7:0] 0 0 1 = capture timer[8:1] 0 1 0 = capture timer[9:2] 0 1 1 = capture timer[10:3] 1 0 0 = capture timer[11:4] 1 0 1 = capture timer[12:5] 1 1 0 = capture timer[13:6] 1 1 1 = capture timer[14:7] bit 3: cap0 16-bit enable 0 = capture 0 16-bit mode is disabled 1 = capture 0 16-bit mode is enabled. capture 1 is disabled and the capture 1 rising and falling regi sters are used as an exten sion to the capture 0 registers ? extending them to 16 bits bit [2:0]: reserved table 16-12. capture interrupt enable (tcapinte) [0x2b] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall enable cap1 rise enable cap0 fall enable cap0 rise enable read/write???? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit 3: cap1 fall enable 0 = disable the capture 1 falling edge interrupt 1 = enable the capture 1 falling edge interrupt bit 2: cap1 rise enable 0 = disable the capture 1 rising edge interrupt 1 = enable the capture 1 rising edge interrupt bit 1: cap0 fall enable 0 = disable the capture 0 falling edge interrupt 1 = enable the capture 0 falling edge interrupt bit 0: cap0 rise enable 0 = disable the capture 0 rising edge interrupt 1 = enable the capture 0 rising edge interrupt confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 41 of 70 16.1.13 capture interrupt status 17.0 interrupt controller the interrupt controller and its associated registers allow the user?s code to respond to an interrupt from almost every functional block in the encore ii devices. the registers associated with the interrupt controller allow interrupts to be disabled either globally or individually. the registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts. the following table lists all interrupts and the priorities that are available in the encore ii devices. 17.1 architectural description an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 17-1 clocking in a ?1?. the interrupt will remain posted until the interrupt is taken or until it is cleared by writing to the appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate int_mskx register). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt which will be taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. it simply prevents a posted interrupt from becoming pending. nested interrupts can be accomplished by reenabling inter- rupts inside an interrupt service routine. to do this, set the ie bit in the flag register. a block diagram of the encore ii interrupt controller is shown in figure 17-1 . table 16-13. capture interrupt status (tcapints) [0x2c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active read/write???? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit 3: cap1 fall active 0 = no event 1 = a falling edge has occurred on cap1 bit 2: cap1 rise active 0 = no event 1 = a rising edge has occurred on cap1 bit 1: cap0 fall active 0 = no event 1 = a falling edge has occurred on cap0 bit 0: cap0 rise active 0 = no event 1 = a rising edge has occurred on cap0 table 17-1. interrupt numbers, priorities, vectors interrupt priority interrupt address name 0 0000h reset 1 0004h por/lvd 2 0008h int0 3 000ch spi transmitter empty 4 0010h spi receiver full 5 0014h gpio port 0 6 0018h gpio port 1 7001chint1 8 0020h ep0 9 0024h ep1 10 0028h ep2 11 002ch usb reset 12 0030h usb active 13 0034h 1-ms interval timer 14 0038h programmable interval timer 15 003ch timer capture 0 16 0040h timer capture 1 17 0044h 16-bit free running timer wrap 18 0048h int2 19 004ch ps2 data low 20 0050h gpio port 2 21 0054h gpio port 3 22 0058h gpio port 4 23 005ch reserved 24 0060h reserved 25 0064h sleep timer table 17-1. interrupt numbers, priorities, vectors (contin- interrupt priority interrupt address name confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 42 of 70 17.2 interrupt processing the sequence of events that occur during interrupt processing is as follows: 1. an interrupt becomes active, either because: ? the interrupt condition occurs (e.g., a timer expires) ? a previously posted interrupt is enabled through an update of an interrupt mask register ? an interrupt is pending and gie is set from 0 to 1 in the cpu flag register. 2. the current executing instruction finishes. 3. the internal interrupt is di spatched, taking 13 cycles. during this time, the following actions occur: he msb and lsb of program counter and flag registers (cpu_pc and cpu_f) are stored onto the program stack by an automatic call instruction (13 cycles) ge nerated during the interrupt acknowledge process. ? the pch, pcl, and flag register (cpu_f) are stored onto the program stack (in that order) by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process ? the cpu_f register is then cleared. since this clears the gie bit to 0, additional interrupts are temporarily disabled ? the pch (pc[15:8]) is cleared to zero ? the interrupt vector is read from the interrupt controller and its value placed into pc l (pc[7:0]). this sets the program counter to point to the appropriate address in the interrupt table (e.g., 000 4h for the por/lvd interrupt) 4. program execution vectors to the interrupt table. typically, a ljmp instruction in the interrupt table sends execution to the user's interrupt service ro utine (isr) for this interrupt 5. the isr executes. note that interrupts are disabled since gie = 0. in the isr, interrupts can be re-enabled if desired by setting gie = 1 (care must be taken to avoid stack overflow). 6. the isr ends with a reti inst ruction which restores the program counter and flag registers (cpu_pc and cpu_f). the restored flag register re-enables interrupts, since gie = 1 again. 7. execution resumes at the next instruction, after the one that occurred before the interrupt. however, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction. 17.3 interrupt latency the time between the assertion of an enabled interrupt and the start of its isr can be calculated from the following equation. latency = time for current inst ruction to finish + time for internal interrupt routine to execute + time for ljmp instruction in interrupt table to execute. for example, if the 5-cycle jmp instruction is executing when an interrupt becomes active, the total number of cpu clock cycles before the isr begins would be as follows: (1 to 5 cycles for jmp to fini sh) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. in the example above, at 24 mhz, 25 clock cycles take 1.042 msec. 17.4 interrupt registers 17.4.1 interrupt clear register the interrupt clear registers (int_clrx) are used to enable the individual interrupt sources? ability to clear posted inter- rupts. when an int_clrx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. therefore, reading these registers gives the user the ability to determine all posted interrupts. interrupt source (timer, gpio, etc.) interrupt tak en or posted interrupt pending interrupt gie interrupt vector mask bit setting d r q 1 priority encoder m8c c o r e interrupt request ... int_mskx int_clrx write cpu_f[0] ... figure 17-1. interrupt controller block diagram confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 43 of 70 17.4.2 interrupt mask registers the interrupt mask registers (int_mskx) are used to enable the individual interrupt sources? ability to create pending inter- rupts. there are four interrupt mask registers (int_msk0, int_msk1, int_msk2, and int_msk3) which may be referred to in general as int_mskx. if cleared, each bit in an int_mskx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_mskx bits are independent of all other int_mskx bits. if an int_mskx bit is set, the interrupt source associated with that mask bit may generate an interrupt that will become a pending interrupt. the enable software interrupt (enswint) bit in int_msk3[7] determines the way an individual bit value written to an int_clrx register is interpreted. when is cleared, writing 1's to an int_clrx register has no effect. however, writing 0's to an int_clrx register, when enswint is cleared, will cause the corresponding inte rrupt to clear. if th e enswint bit is set, any 0's written to the int_clrx registers are ignored. however, 1's written to an int_clrx register, while enswint is set, will cause an interrupt to post for the corresponding interrupt. software interrupts can aid in debugging interrupt service routines by eliminat ing the need to create system level inter- actions that are sometimes necessary to create a hardware- only interrupt. table 17-2. interrupt clear 0 (int_clr0) [0xda] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for t he corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt table 17-3. interrupt clear 1 (int_clr1) [0xdb] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for t he corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will po st the corresponding hardware interrupt table 17-4. interrupt clear 2 (int_clr2) [0xdc] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved gpio port 4 gpio port 3 gpio port 2 ps/2 data low int2 16-bit counter wrap tcap1 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for t he corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 44 of 70 table 17-5. interrupt mask 3 (int_msk3) [0xde] [r/w] bit # 7 6 5 4 3 2 1 0 field enswint reserved read/write r/w ? ? ? ? ? ? ? default 0 0 0 0 00 0 0 bit 7: enable software interrupt (enswint) 0= disable. writing 0's to an int_clrx register, when enswin t is cleared, will cause the corresponding interrupt to clear 1= enable. writing 1's to an int_clrx register, when enswin t is set, will cause the corresponding interrupt to post. bit [6:0]: reserved table 17-6. interrupt mask 2 (int_msk2) [0xdf] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep timer int enable gpio port 4 int enable gpio port 3 int enable gpio port 2 int enable ps/2 data low int enable int2 int enable 16-bit counter wrap int enable tcap1 int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: sleep timer interrupt enable 0 = mask sleep timer interrupt 1 = unmask sleep timer interrupt bit 6: gpio port 4 interrupt enable 0 = mask gpio port 4 interrupt 1 = unmask gpio port 4 interrupt bit 5: gpio port 3 interrupt enable 0 = mask gpio port 3 interrupt 1 = unmask gpio port 3 interrupt bit 4: gpio port 2 interrupt enable 0 = mask gpio port 2 interrupt 1 = unmask gpio port 2 interrupt bit 3: ps/2 data low interrupt enable 0 = mask ps/2 data low interrupt 1 = unmask ps/2 data low interrupt bit 2: int2 interrupt enable 0 = mask int2 interrupt 1 = unmask int2 interrupt bit 1: 16-bit counter wrap interrupt enable 0 = mask 16-bit counter wrap interrupt 1 = unmask 16-bit counter wrap interrupt bit 0: tcap1 interrupt enable 0 = mask tcap1 interrupt 1 = unmask tcap1 interrupt confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 45 of 70 table 17-7. interrupt mask 1 (int_msk1) [0xe0] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 int enable prog interval timer int enable 1ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: tcap0 interrupt enable 0 = mask tcap0 interrupt 1 = unmask tcap0 interrupt bit 6: prog interval timer interrupt enable 0 = mask prog interval timer interrupt 1 = unmask prog interval timer interrupt bit 5: 1-ms timer interrupt enable 0 = mask 1-ms interrupt 1 = unmask 1-ms interrupt bit 4: usb active interrupt enable 0 = mask usb active interrupt 1 = unmask usb active interrupt bit 3: usb reset interrupt enable 0 = mask usb reset interrupt 1 = unmask usb reset interrupt bit 2: usb ep2 interrupt enable 0 = mask ep2 interrupt 1 = unmask ep2 interrupt bit 1: usb ep1 interrupt enable 0 = mask ep1 interrupt 1 = unmask ep1 interrupt bit 0: usb ep0 interrupt enable 0 = mask ep0 interrupt 1 = unmask ep0 interrupt table 17-8. interrupt mask 0 (int_msk0) [0xe1] [r/w] bit # 7 6 5 4 3 2 1 0 field int1 int enable gpio port 1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/ lvd int enable reset int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: int1 interrupt enable 0 = mask int1 interrupt 1 = unmask int1 interrupt bit 6: gpio port 1 interrupt enable 0 = mask gpio port 1 interrupt 1 = unmask gpio port 1 interrupt bit 5: gpio port 0 interrupt enable 0 = mask gpio port 0 interrupt 1 = unmask gpio port 0 interrupt bit 4: spi receive interrupt enable 0 = mask spi receive interrupt 1 = unmask spi receive interrupt bit 3: spi transmit interrupt enable 0 = mask spi transmit interrupt 1 = unmask spi transmit interrupt bit 2: int0 interrupt enable 0 = mask int0 interrupt 1 = unmask int0 interrupt bit 1: por/lvd interrupt enable 0 = mask por/lvd interrupt 1 = unmask por/lvd interrupt bit 0: reset interrupt enable 0 = mask reset interrupt 1 = unmask reset interrupt confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 46 of 70 17.4.3 interrupt vector clear register 18.0 usb/ps2 transceiver although the usb transceiver has features to assist in inter- facing to ps/2 these features are not controlled using these registers. these registers only control the usb interfacing features. ps/2 interfacing options are controlled by the d+/d- gpio configuration register (see section table 14.2.15 ). 18.1 usb transceiver configuration table 17-9. interrupt vector clear register (int_vc) [0xe2] [r/w] bit # 7 6 5 4 3 2 1 0 field pending interrupt [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the interrupt vector clear register (int_vc) holds the interrupt vector for the highest priority pending interrupt when read, a nd when written will clear all pending interrupts bit [7:0]: pending interrupt [7:0] 8-bit data value holds the interrupt vector for the highest priori ty pending interrupt. writing to this register will clear all pending interrupts. table 18-1. usb transceiver configure register (usbxcr) [0x74] [r/w] bit # 7 6 5 4 3 2 1 0 field usb pull-up enable reserved usb force state read/write r/w ? ? ? ? ? ? r/w default 0 0 0 0 00 0 0 bit 7: usb pull-up enable 0 = disable the pull-up resistor on d- 1 = enable the pull-up resistor on d-. this pull-up is to vdd if vreg is not enabled or to the internally generated 3.3v when vreg is enabled bit [6:1]: reserved bit 0: usb force state this bit allows the state of the usb i/o pins d- and d+ to be forced to a state while usb is enabled 0 = disable usb force state 1 = enable usb force state. allows the d- and d+ pins to be controlled by p1.1 and p1.0 respectively when the usbio is in usb mode. refer to section 14.2.15 for more information confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 47 of 70 19.0 usb regulator output 19.1 vreg control 20.0 usb serial interface engine (sie) the sie allows the microcontroller to communicate with the usb host at low-speed data rates (1.5mbps). the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: ? translate the encoded received data and format the data to be transmitted on the bus. ? crc checking and generation. flag the microcontroller if errors exist during transmission. ? address checking. ignore the transactions not addressed to the device. ? send appropriate ack/nak/stall handshakes. ? token type identification (setup, in, or out). set the appropriate token bit once a valid token is received. ? place valid received data in the appropriate endpoint fifos. ? send and update the data toggle bit (data1/0). ? bit stuffing/unstuffing. firmware is required to handle t he rest of the usb interface with the following tasks: ? coordinate enumeration by decoding usb device requests. ? fill and empty the fifos. ? suspend/resume coordination. ? verify and select data toggle values. table 19-1. vreg control register (vregcr) [0x73] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved keep alive vreg enable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 00 0 0 bit [7:2]: reserved bit 1: keep alive keep alive when set allows the voltage regulator to s ource up to 20a of current when it is disabled 0 = disabled 1 = enabled bit 0: vreg enable this bit turns on the 3.3v voltage regulator. the voltage regulator only functions within specifications when vcc is above 4.35 v. this block should not be enabled when vcc is below 4.35v?althou gh no damage or irregularities will occur if it is enabled below 4.35v 0 = disable the 3.3v voltage regu lator output on the vreg/p1.2 pin 1 = enable the 3.3v voltage regulator output on the vreg /p1.2 pin. gpio functionality of p1.2 is disabled note: use of the alternate drive on pins p1.3 - p1.6 requires that the vreg enable bit be set to enable the regulator and pro- vide the alternate voltage confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 48 of 70 21.0 usb device 21.1 usb device address 21.2 endpoint 0, 1, and 2 count table 21-1. usb device address (usbcr) [0x40] [r/w] bit # 7 6 5 4 3 2 1 0 field usb enable device address[6:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: usb enable this bit must be enabled by firmware before the serial in terface engine (sie) will respond to usb traffic at the address specif ied in device address [6:0] 0 = disable usb device address 1 = enable usb device address bit [6:0]: device address [6:0] these bits must be set by firmware during the usb enumeratio n process (i.e., setaddress) to the non-zero address assigned by the usb host. table 21-2. endpoint 0, 1, and 2 count (ep0cnt ? ep2cnt) [0x41, 0x43, 0x45] [r/w] bit # 7 6 5 4 3 2 1 0 field data toggle data valid reserved byte count[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: data toggle this bit selects the data packet's toggle state. for in transacti ons, firmware must set this bit to the select the transmitted data toggle. for out or setup transactions, the hardware sets this bit to the state of the received data toggle bit. 0 = data0 1 = data1 bit 6: data valid this bit is used for out and setup tokens only. this bit is clea red to ?0? if crc, bitstuff, or pid errors have occurred. this bit does not update for some endpoint mode settings 0 = data is invalid. if enabled, the endpoint in terrupt will occur even if invalid data is received 1 = data is valid bit [5:4]: reserved bit [3:0]: byte count bit [3:0] byte count bits indicate the number of data bytes in a transac tion: for in transactions, firmware loads the count with the numb er of bytes to be transmitted to the host from the endpoint fifo. va lid values are 0 to 8 inclusive. for out or setup transactions , the count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2?10 inclusiv e. for endpoint 0 count register, whenever the count updates fr om a setup or out transaction, the count register locks and cannot be written by the cpu. reading the register unlocks it. this prevents firm ware from overwriting a status update on. confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 49 of 70 21.3 endpoint 0 mode because both firmware and the sie are allowed to write to the endpoint 0 mode and count registers the sie provides an interlocking mechanism to prevent accidental overwriting of data. when the sie writes to these registers they are locked and the processor cannot write to them until after it has read them. writing to this register clears the upper four bits regardless of the value written. table 21-3. endpoint 0 mo de (ep0mode) [0x44] [r/w] bit # 7 6 5 4 3 2 1 0 field setup received in received out received ack?d trans mode[3:0] read/write r/c [3] r/c [3] r/c [3] r/c [3] r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: setup received this bit is set by hardware when a valid setup packet is received . it is forced high from the start of the data packet phase of the setup transactions until the end of the data phase of a control write transfer and cannot be cleared during this interval. while this bit is set to ?1?, the cpu cannot write to the ep0 fifo. this prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data. this bit is cleared by any non- locked writes to the register. 0 = no setup received 1 = setup received bit 6: in received this bit when set indicates a valid in packet has been received. this bit is updated to ?1? after the host acknowledges an in d ata packet.when clear, it indicates either no in has been received or that the host didn?t acknowledge the in data by sending ack handshake. this bit is cleared by any non- locked writes to the register. 0 = no in received 1 = in received bit 5: out received this bit when set indicates a valid out packet has been received and acked. this bit is updated to ?1? after the last received packet in an out transaction. when clear, it indicates no out received. this bit is cleared by any non- locked writes to the register. 0 = no out received 1 = out received bit 4: ack?d transaction the ack?d transaction bit is set whenever the sie engages in a tr ansaction to the register?s endpoint that completes with a ack packet. this bit is cleared by any non- locked writes to the register 1 = the transaction completes with an ack 0 = the transaction does not complete with an ack bit [3:0]: mode [3:0] the endpoint modes determine how the sie responds to usb traf fic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie will change the mode of that endpoint as a result of host packets to the endpoint. confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 50 of 70 21.4 endpoint 1 and 2 mode 21.4.1 endpoint 0, 1, and 2 data buffer the three data buffers used to hold data for both in and out transactions. each data buffer is 8 bytes long. the reset values of the endpoint data registers are unknown. unlike past encore parts the usb data buffers are only accessible in the i/o space of the processor. table 21-4. endpoint 1 and 2 mode ( ep1mode ? ep2mode) [0x45, 0x46] [r/w] bit # 7 6 5 4 3 2 1 0 field stall reserved nak int enable ack?d transaction mode[3:0] read/write r/w r/w r/w r/c (note 1) r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: stall when this bit is set the sie will stall an out packet if the mode bits are set to ack-out, and the sie will stall an in packet if the mode bits are set to ack-in. this bit must be clear for all other modes bit 6: reserved bit 5: nak int enable this bit when set causes an endpoint interrupt to be gener ated even when a transfer completes with a nak. unlike encore, encore ii family members do not generate an endpoint in terrupt under these conditions unless this bit is set 0 = disable interrupt on nak?d transactions 1 = enable interrupt on nak?d transaction bit 4: ack?d transaction the ack?d transaction bit is set whenever the sie engages in a tr ansaction to the register?s endpoint that completes with an ack packet. this bit is cleared by any writes to the register 0 = the transaction does not complete with an ack 1 = the transaction completes with an ack bit [3:0]: mode [3:0] the endpoint modes determine how the sie responds to usb traffic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie will change the mode of that endpoint as a result of host packets to the endpoi nt. table 21-5. endpoint 0 data (ep0data) [0x50-0x57] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 0 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57 table 21-6. endpoint 1 data (ep1data) [0x58-0x5f] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 1 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5f table 21-7. endpoint 2 data (ep2data) [0x60-0x67] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 2 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 51 of 70 22.0 usb mode tables mode column the 'mode' column contains t he mnemonic names given to the modes of the endpoint. the mode of the endpoint is deter- mined by the four-bit binaries in the 'encoding' column as discussed below. the status in and status out represent the status in or out stage of the control transfer. encoding column the contents of the 'encoding' column represent the mode bits [3:0] of the endpoint mode registers ( table 21-3 and table 21-4 ). the endpoint modes determine how the sie responds to different tokens that the host sends to the endpoints. for example, if the mode bits [3:0] of the endpoint 0 mode register are set to '0001', which is nak in/out mode, the sie will send an ack handshake in response to setup tokens and nak any in or out tokens. setup, in, and out columns depending on the mode specified in the 'encoding' column, the 'setup', 'in', and 'out' columns contain the sie's responses when the endpoint receives setup, in, and out tokens, respectively. a 'check' in the out column means that upon receiving an out token the sie checks to s ee whether the out is of zero length and has a data toggle (data1/0) of 1. if these condi- tions are true, the sie responds with an ack. if any of the above conditions is not met, the sie will respond with either a stall or ignore. a 'tx count' entry in the in column means that the sie will transmit the number of bytes specified in the byte count bit [3:0] of the endpoint count register ( table 21-2 ) in response to any in token. mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint. used by data and control endpoints nak in/out 0001 accept nak nak nak in and out token. control endpoint only status out only 0010 accept stall check stall in and ack zero byte out. control endpoint only stall in/out 0011 accept stall stall stall in and out token. control endpoint only status in only 0110 accept tx0 byte stall stall out and send zero byte data for in token. con- trol endpoint only ack out ? status in 1011 accept tx0 byte ack ack the out token or send zero byte data for in token. control endpoint only ack in ? status out 1111 accept tx count check respond to in data or status out. control endpoint only nak out 1000 ignore ignore nak send nak handshake to out token. data endpoint only ack out (stall = 0) 1001 ignore ignore ack this mode is changed by the sie to mode 1000 on issu- ance of ack handshake to an out. data endpoint only ack out (stall = 1) 1001 ignore ignore stall stall the out transfer nak in 1100 ignore nak ignore send nak handshake for in token. data endpoint only ack in (stall = 0) 1101 ignore tx count ignore this mode is changed by the sie to mode 1100 after re- ceiving ack handshake to an in data. data endpoint only ack in (stall = 1) 1101 ignore stall ignore stall the in transfer. data endpoint only reserved 0101 ignore ignore ignore these modes ar e not supported by sie. firmware should not use this mode in control and data endpoints reserved 0111 ignore ignore ignore reserved 1010 ignore ignore ignore reserved 0100 ignore ignore ignore reserved 1110 ignore ignore ignore confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 52 of 70 23.0 details of mode for differing traffic conditions control endpoint sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo disabled 0000 x x x x ignore all stall_in_out 0011 setup >10 x x junk ignore 0011 setup <=10 invalid x junk ignore 0011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0011 in x x x stall stall in 0011 out >10 x x ignore 0011 out <=10 invalid x ignore 0011 out <=10 valid x stall stall out nak_in_out 0001 setup >10 x x junk ignore 0001 setup <=10 invalid x junk ignore 0001 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0001 in x x x nak nak in 0001 out >10 x x ignore 0001 out <=10 invalid x ignore 0001 out <=10 valid x nak nak out ack_in_status_out 1111 setup >10 x x junk ignore 1111 setup <=10 invalid x junk ignore 1111 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1111 in x x x tx host not ack'd 1111 in x x x tx 1 1 0001 yes host ack'd 1111 out >10 x x ignore 1111 out <=10 invalid x ignore 1111 out <=10, <>2 valid x stall 0011 yes bad status 1111 out 2 valid 0 stall 0011 yes bad status 1111 out 2 valid 1 ack 1 1 0010 1 1 2 yes good status status_out 0010 setup >10 x x junk ignore 0010 setup <=10 invalid x junk ignore 0010 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0010 in x x x stall 0011 yes stall in 0010 out >10 x x ignore 0010 out <=10 invalid x ignore 0010 out <=10, <>2 valid x stall 0011 yes bad status 0010 out 2 valid 0 stall 0011 yes bad status 0010 out 2 valid 1 ack 1 1 1 1 2 yes good status confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 53 of 70 ack_out_status_in 1011 setup >10 x x junk ignore 1011 setup <=10 invalid x junk ignore 1011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1011 in x x x tx 0 host not ack'd 1011 in x x x tx 0 1 1 0011 yes host ack'd 1011 out >10 x x junk ignore 1011 out <=10 invalid x junk ignore 1011 out <=10 valid x ack 1 1 0001 update 1 update data yes good out status_in 0110 setup >10 x x junk ignore 0110 setup <=10 invalid x junk ignore 0110 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0110 in x x x tx 0 host not ack'd 0110 in x x x tx 0 1 1 0011 yes host ack'd 0110 out >10 x x ignore 0110 out <=10 invalid x ignore 0110 out <=10 valid x stall 0011 yes stall out data out endpoints sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo ack out (stall bit = 0) 1001 in x x x ignore 1001 out >max x x junk ignore 1001 out <=max invalid invalid junk ignore 1001 out <=max valid valid ack 1 1000 update 1 update data yes ack out ack out (stall bit = 1) 1001 in x x x ignore 1001 out >max x x ignore 1001 out <=max invalid invalid ignore 1001 out <=max valid valid stall stall out nak out 1000 in x x x ignore 1000 out >max x x ignore 1000 out <=max invalid invalid ignore 1000 out <=max valid valid nak if enabled nak out 23.0 details of mode for differing traffic conditions (continued) confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 54 of 70 data in endpoints sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo ack in (stall bit = 0) 1101 out x x x ignore 1101 in x x x host not ack'd 1101 in x x x tx 1 1100 yes host ack'd ack in (stall bit = 1) 1101 out x x x ignore 1101 in x x x stall stall in nak in 1100 out x x x ignore 1100 in x x x nak if enabled nak in 24.0 register summary addr name 7 6 5 4 3 2 1 0 r/w default 00 p0data p0.7 p0.6/ti o1 p0.5/ti o0 p0.4/int 2 p0.3/int 1 p0.2/int0 p0.1/cl kout p0.0/cl kin bbbbbbbb 00000000 01 p1data p1.7 p1.6/s miso p1.5/s mosi p1.4/sc lk p1.3/ss el p1.2/vre g p1.1/d- p1.0/d+ bbbbbbbb 00000000 02 p2data p2.7 ? p2.2 p2.1 ? p2.0 bbbbbbbb 00000000 03 p3data p3.7 ? p3.2 p3.1 ? p3.0 bbbbbbbb 00000000 04 p4data res p4.3 ? p4.0 ----bbbb 00000000 05 p00cr res int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 06 p01cr clk output int enable int act low ttl thresh high sink open drain pull-up enable output enable bbbbbbbb 00000000 07 ? 09 p02cr ? p04cr res int enable int act low ttl thresh res open drain pull-up enable output enable -bbbbbbb 00000000 0a ? 0b p05cr ? p06cr tio output int enable int act low ttl thresh res open drain pull-up enable output enable bbbbbbbb 00000000 0c p07cr res int enable int act low ttl thresh res open drain pull-up enable output enable -bbbbbbb 00000000 0d p10cr res int enable int act low res ps/2 pull-up enable output enable bbb---bb 00000000 0e p11cr res int enable int act low res open drain res output enable bbb--bbb 00000000 0f p12cr clk output int enable int act low ttl thresh res open drain pull-up enable output enable bbbbbbbb 00000000 10 p13cr res int enable int act low 3.3v drive high sink open drain pull-up enable output enable -bbbbbbb 00000000 11 - 13 p14cr ? p16cr spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable bbbbbbbb 00000000 14 p17cr res int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 15 p2cr res int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 23.0 details of mode for differing traffic conditions (continued) confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 55 of 70 16 p3cr res int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 17 p4cr res int enable int act low ttl thresh res open drain pull-up enable output enable -bbb-bbb 00000000 20 frtmrl free running timer [7:0] bbbbbbbb 00000000 21 frtmrh free running timer [15:8] bbbbbbbb 00000000 22 tcap0r capture 0 rising [7:0] bbbbbbbb 00000000 23 tcap1r capture 1 rising [7:0] bbbbbbbb 00000000 24 tcap0f capture 0 falling [7:0] bbbbbbbb 00000000 25 tcap1f capture 1 falling [7:0] bbbbbbbb 00000000 26 pitmrl prog interval timer [7:0] bbbbbbbb 00000000 27 pitmrh res prog interval timer [11:8] ----bbbb 00000000 28 pirl prog interval [7:0] bbbbbbbb 00000000 29 pirh res prog interval [11:8] ----bbbb 00000000 2a tmrcr first edge hold 8-bit capture prescale cap0 16bit enable res bbbbb--- 00000000 2b tcapinte res cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 2c tcapints reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 30 cpuclkc r res usb clk /2 disable usb clk select res cpu clk select -bb--bbb 00010000 31 itmrclk cr tcapclk divider tcapclk select itmrclk divider itmrclk select bbbbbbbb 10001111 32 clkiocr res xosc select xosc enable eftb disable clkout select ---bbbbb 00000000 34 iosctr foffset[2:0] gain[4:0] bbbbbbbb 000ddddd 35 xosctr res xosc xgm [2:0] res mode ---bbb-b 000ddd0d 36 lposctr 32 khz low power res 32 khz bias trim [1:0] 32 khz freq trim [3:0] b-bbbbbb dddddddd 39 osclckc r res fine tune only usb osclock disable ------bb 00000000 3c spidata spidata[7:0] bbbbbbbb 00000000 3d spicr swap lsb first comm mode cpol cpha sclk select bbbbbbbb 00000000 40 usbcr usb enable device address[6:0] bbbbbbbb 00000000 24.0 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 56 of 70 41 ep0cnt data to g g l e data valid res byte count[3:0] bbbbbbbb 00000000 42 ep1cnt data to g g l e data valid res byte count[3:0] bbbbbbbb 00000000 43 ep2cnt data to g g l e data valid res byte count[3:0] bbbbbbbb 00000000 44 ep0mode setup rcv?d in rcv?d out rcv?d ack?d trans mode[3:0] ccccbbbb 00000000 45 ep1mode stall res nak int enable ack?d trans mode[3:0] b-bbbbbb 00000000 46 ep2mode stall res nak int enable ack?d trans mode[3:0] b-bbbbbb 00000000 50 ? 57 ep0data endpoint 0 data buffer [7:0] bbbbbbbb ???????? 58 ? 5f ep1data endpoint 1 data buffer [7:0] bbbbbbbb ???????? 60 ? 67 ep2data endpoint 2 data buffer [7:0] bbbbbbbb ???????? 73 vregcr res keep alive vreg enable ------bb 00000000 74 usbxcr usbpul l-up enable res usb force state b------b 00000000 da int_clr0 gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lv d bbbbbbbb 00000000 db int_clr1 tcap0 prog interval timer 1ms timer usb active usb reset usb ep2 usb ep1 usb ep0 bbbbbbbb 00000000 dc int_clr2 res gpio port 4 gpio port 3 gpio port 2 ps/2 data low int2 16-bit counter wrap tcap1 bbbbbbbb 00000000 de int_msk3 enswi nt res b------- 00000000 df int_msk2 sleep timer int enable gpio port 4 int enable gpio port 3 int enable gpio port 2 int enable ps/2 data low int enable int2 int enable 16-bit counter wrap int enable tcap1 int enable bbbbbbbb 00000000 e0 int_msk1 tcap0 int enable prog interval timer int enable 1ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable bbbbbbbb 00000000 e1 int_msk0 int1 int enable gpio port 1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/ lvd int enable reset int enable bbbbbbbb 00000000 e2 int_vc pending interrupt [7:0] bbbbbbbb 00000000 e3 reswdt reset watchdog timer [7:0] wwwwwwww 00000000 -- cpu_a temporary register t1 [7:0] -------- 00000000 -- cpu_x x[7:0] -------- 00000000 -- cpu_pcl program counter [7:0] -------- 00000000 -- cpu_pch program counter [15:8] -------- 00000000 -- cpu_sp stack pointer [7:0] -------- 00000000 24.0 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 57 of 70 note: in the r/w column, b = both read and write r = read only w = write only c = read/clear res = reserved ? = unknown d = calibration value. should not change during normal use f7 cpu_f super carry zero global ie ----rwww 00000000 ff cpu_scr gies res wdrs pors sleep res res stop r-ccb--b 00010000 1e0 osc_cr0 res no buzz sleep timer [1:0] cpu speed [2:0] bbbbbbbb 00000000 1e3 lvdcr res res porlev[1:0] res vm[3:0] --bb-bbb 00000000 1eb eco_tr sleep duty cycle [1:0] res bb------ 00000000 1e4 vltcmp res lvd ppor ------rr 00000000 24.0 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 58 of 70 25.0 absolute maximum ratings storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied ..... ?0c to +70c supply voltage on v cc relative to v ss ......... ?0.5v to +7.0v dc input voltage................................ ?0.5v to + v cc + 0.5v dc voltage applied to outputs in high-z state ....................................... ?0.5v to + v cc + 0.5v maximum total sink output current into port 0 and 1 and pins............................................................. 70 ma maximum total source output current into gpio pins30 ma maximum on-chip po wer dissipation on any gpio pin......................................................... 50 mw power dissipation .................................................... 300 mw static discharge voltage ............................................ 2200 v latch-up current ...................................................... 200 ma 26.0 dc characteristics parameter description conditions min. typical max. unit general v cc1 operating voltage no usb activity, cpu speed <= 12 mhz 4.0 5.25 v v cc2 operating voltage usb activity, cpu speed <= 12 mhz. flash programming 4.35 5.25 v v cc3 operating voltage usb activity, cpu speed <= 24 mhz 4.75 5.25 v t fp operating temp flash programming 0 70 c i cc1 v cc operating supply current v cc = 5.5v, no gpio loading, 24 mhz 40 ma i cc2 v cc operating supply current v cc = 5.5v, no gpio loading, 6 mhz 10 ma i sb1 standby current internal and external oscillators, bandgap, flash, cpu clock, timer clock, usb clock all disabled 10 ua low-voltage and power-on reset v lvr low-voltage reset trip voltage 2.6v worst case. data will be updated later tbd tbd v 3.3v regulator i vreg max regulator output current v cc >= 4.35v 125 ma i fa keep alive current when regulator is disabled with ?keep alive? enabled 20 ua v reg1 v reg output voltage v cc >= 4.35v, 0 < temp < 40c, i vreg <= 125 ma (3.3v 8%) 3.0 3.6 v v reg2 v reg output voltage v cc >= 4.35v, 0 < temp < 40c, i vreg <= 25 ma (3.3v 4%) 3.15 3.45 v usb interface v on static output high 15k 5% ohm to v ss 2.8 3.6 v v off static output low r up is enabled 0.3 v v di differential input sensitivity 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2 v c in transceiver capacitance 20 pf i io hi-z state data line leakage 0v < v in < 3.3v ?10 10 ua ps/2 interface v olp static output low sdata or sclk pins 0.4 v r ps2 internal ps/2 pull-up resistance sdata, sclk pins, ps/2 enabled 3 7 k ? general purpose i/o interface r up pull-up resistance 4 12 k ? v icr input threshold voltage low, cmos mode low to high edge 40% 65% v cc confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 59 of 70 v icf input threshold voltage low, cmos mode high to low edge 30% 55% v cc v hc input hysteresis voltage, cmos mode high to low edge 3% 10% v cc v ilttl input low voltage, ttl mode 0.52 v v ihttl input high voltage, ttl mode 3.1 v v ol1 output low voltage, high drive [4] i ol1 = 50 ma 0.8 v v ol2 output low voltage, high drive i ol1 = 25 ma 0.4 v v ol3 output low voltage, low drive i ol2 = 8 ma 0.4 v v oh output high voltage i oh = 2 ma v cc ? 0.5 v 27.0 ac characteristics parameter description conditions min. typical max. unit clock t eclkdc external clock duty cycle 45 55 % t eclk1 t eclk2 external clock frequency external clock frequency external clock is the source of the cpuclk external clock is not the source of the cpuclk 0.187 0 24 24 mhz mhz usb driver t r1 transistion rise time c load = 200pf 75 ns t r2 transistion rise time c load = 600pf 300 ns t f1 transistion fall time c load = 200pf 75 ns t f2 transistion fall time c load = 600pf 300 ns t r rise/fall time matching 80 125 % v crs output signal crossover voltage 1.3 2.0 v usb data timing t drate low-speed data rate ave. bit rate (1.5 mbps 1.5%) 1.4775 1.5225 mbps t djr1 receiver data jitter tolerance to next transition ?75 75 ns t djr2 receiver data jitter tolerance to pair transition ?45 45 ns t deop differential to eop transistion skew ?40 100 ns t eopr1 eop width at receiver rejects as eop 330 ns t eopr2 eop width at receiver accept as eop 675 ns t eopt source eop width 1.25 1.5 us t udj1 differential driver jitter to next transition ?95 95 ns t udj2 differential driver jitter to pair transition ?95 95 ns t lst width of se0 during diff. transition 210 ns non-usb mode driver characteristics t fps2 sdata/sck transition fall time 50 300 ns spi timing t smck spi master clock rate f clk /3 2 mhz t ssck spi slave clock rate 2.2 mhz t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ns note: 4. available only on p2.7, p3.7, p0.0, p0.1 and power supply is 5.0v range. 26.0 dc characteristics (continued) parameter description conditions min. typical max. unit general confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 60 of 70 t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ns t mdo master data output time sck to data valid ?25 50 ns t mdo1 master data output time, first bit with cpha = 1 time before leading sck edge 100 ns t msu master input data set-up time 50 ns t mhd master input data hold time 50 ns t ssu slave input data set-up time 50 ns t shd slave input data hold time 50 ns t sdo slave data output time sck to data valid 100 ns t sdo1 slave data output time, first bit with cpha = 1 time after ss low to data valid 100 ns t sss slave select set-up time before first sck edge 150 ns t ssh slave select hold time after last sck edge 150 ns 27.0 ac characteristics (continued) parameter description conditions min. typical max. unit figure 27-1. clock timing figure 27-2. usb data signal timing figure 27-3. receiver jitter tolerance clock t cyc t cl t ch 90% 10% 90% 10% d ? d + t r t f v crs v oh v ol differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 61 of 70 figure 27-4. differential to eop transition skew and eop width figure 27-5. differential data jitter figure 27-6. spi master timing, cpha = 1 t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 62 of 70 figure 27-7. spi slave timing, cpha = 1 figure 27-8. spi master timing, cpha = 0 msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 63 of 70 figure 27-9. spi slave timing, cpha = 0 msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 64 of 70 28.0 ordering information ordering code flash size ram size package type cy7c63923-pvxc 8k 256 48-ssop cy7c63913-pxc 8k 256 40-pdip cy7c63903-pvxc 8k 256 28-ssop cy7c63923-xwc 8k 256 die cy7c63823-pxc 8k 256 24-pdip cy7c63823-sxc 8k 256 24-soic cy7c63823-qxc 8k 256 24-qsop cy7c63813-pxc 8k 256 18-pdip cy7c63813-sxc 8k 256 18-soic cy7c63803-sxc 8k 256 16-soic cy7c63801-pxc 4k 256 16-pdip cy7c63801-sxc 4k 256 16-soic cy7c63310-pxc 3k 128 16-pdip cy7c63310-sxc 3k 128 16-soic 29.0 package diagrams 16-lead (300-mil) molded dip p1 51-85009-*a confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 65 of 70 29.0 package diagrams (continued) pin 1 id 0~8 16 lead (150 mil) soic 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 16-lead (150-mil) soic s16.15 51-85068-*b 51-85010-*a 18-lead (300-mil) molded dip p3 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 66 of 70 29.0 package diagrams (continued) pin 1 id seating plane 0.447[11.353] 0.463[11.760] 18 lead (300 mil) soic - s3 1 9 10 18 * * * dimensions in inches[mm] min. max. 0.291[7.391] 0.300[7.620] 0.394[10.007] 0.419[10.642] 0.050[1.270] typ. 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0.299] 0.0091[0.231] 0.0125[0.317] 0.015[0.381] 0.050[1.270] 0.013[0.330] 0.019[0.482] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s18.3 standard pkg. sz18.3 lead free pkg. 18-lead (300-mil) molded soic s3 51-85023-*b pin 1 id seating plane 0.597[15.163] 0.615[15.621] 24 lead (300 mil) soic - s13 1 12 13 24 * * * dimensions in inches[mm] min. max. 0.291[7.391] 0.300[7.620] 0.394[10.007] 0.419[10.642] 0.050[1.270] typ. 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0.299] 0.0091[0.231] 0.0125[0.317] 0.015[0.381] 0.050[1.270] 0.013[0.330] 0.019[0.482] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s24.3 standard pkg. sz24.3 lead free pkg. package weight 0.65gms 51-85025-*b 24-lead (300-mil) soic s13 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 67 of 70 29.0 package diagrams (continued) 51-85013*b 24 lead (300 mil) pdip?p13 0.033 0.228 0.150 0.337 0.053 0.004 0.025 0.008 0.016 0.007 0-8 ref. 0.344 0.157 0.244 bsc. 0.012 0.010 0.069 0.034 0.010 seating plane max. dimensions in inches min. pin 1 id 1 12 24 13 0.004 51-85055-*b 24-lead qsop o241 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 68 of 70 29.0 package diagrams (continued) 28-lead (5.3 mm) shrunk small outline package o28 51-85079-*c 51-85019-*a 40-lead (600-mil) molded dip p17 confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 69 of 70 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. psoc is a trademark of cypress microsystems. encore is a tr ademark of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. 29.0 package diagrams (continued) 48-lead shrunk small outline package o48 51-85061-*c confidential preliminary cy7c63310 cy7c638xx cy7c639xx document 38-08035 rev. *c page 70 of 70 document history page document title: cy7c63310/cy7c638xx/cy7c639xx encore ? ii low-speed usb peripheral controller document number: 38-08035 rev. ecn no. issue date orig. of change description of change ** 131323 12/11/03 xgr new data sheet *a 221881 see ecn kku added register descriptions and package information, changed from advance information to preliminary *b 271232 see ecn bon reformatted updated with the latest information *c 299179 see ecn bon corrected 24-pdip pinout typo in table 5.1 added table 10-1 . updated table 9-5 , table 10-4 , ta ble 13 -1 , table 17-2 , table 17-4 , table 17-6 . and table 15-2 . added various updates to the gpio section (section 14.0). corrected ta ble 15 -3 . corrected figure 27-6 and figure 27-7 . added the 16-pin pdip package diagram (section 29.0). |
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